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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/8723
Title: Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Authors: Kumar Kaushik, Brajesh
Sarkar S.
Agarwal R.P.
Published in: Integration, the VLSI Journal
Abstract: This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent Ï€-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely. © 2006 Elsevier B.V. All rights reserved.
Citation: Integration, the VLSI Journal (2007), 40(4): 394-405
URI: https://doi.org/10.1016/j.vlsi.2006.06.001
http://repository.iitr.ac.in/handle/123456789/8723
Issue Date: 2007
Keywords: Distributed RLC interconnect
Interconnect modeling
Propagation delay
ISSN: 1679260
Author Scopus IDs: 57021830600
7403239706
7402481365
Author Affiliations: Kaushik, B.K., Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee, Uttaranchal 247667, India
Sarkar, S., Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee, Uttaranchal 247667, India
Agarwal, R.P., Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee, Uttaranchal 247667, India
Corresponding Author: Kaushik, B.K.; Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee, Uttaranchal 247667, India; email: brajesh_k_k@yahoo.com
Appears in Collections:Journal Publications [ECE]

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