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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/8506
Title: On-chip measurement of rise/fall gate delay using reconfigurable ring oscillator
Authors: Das B.P.
Onodera H.
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs
Abstract: In this brief, a new technique to measure the on-chip rise/fall delay of an individual gate is presented. In the proposed technique, the rise/fall gate delay is measured using the duty cycle of a reconfigurable ring oscillator (RRO). A set of linear equations is formed with the different configuration settings of the RRO, relating the rise/fall delay of all the gates in the path of the RRO to the positive/negative duty cycle of the undivided RRO. The high-frequency undivided RRO signal is needed for this type of measurement as it preserves the rise/fall delay of an individual gate. However, it is difficult to bring the high-frequency undivided RRO signal outside the chip due to the frequency limitation of the output pad. The high-frequency RRO signal is subsampled by a clock that is generated from an on-chip phase-locked loop to make it low frequency. The rise and fall delays of an individual gate can be calculated from the difference of the duty cycle of the subsampled RRO signal at two different configurations of the RRO. The proposed concept is validated in a test chip that is fabricated in an industrial 65-nm technology node. © 2014 IEEE.
Citation: IEEE Transactions on Circuits and Systems II: Express Briefs (2014), 61(3): 183-187
URI: https://doi.org/10.1109/TCSII.2013.2296118
http://repository.iitr.ac.in/handle/123456789/8506
Issue Date: 2014
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Duty cycle
On-chip measurement of rise/fall gate delay
Reconfigurable ring oscillator (RRO)
Subsampling technique
ISSN: 15497747
Author Scopus IDs: 24472836100
7202438710
Author Affiliations: Das, B.P., Department of Communications and Computer Engineering, Kyoto University, Kyoto 606-8501, Japan, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh 15213-3890, United States
Onodera, H., Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan, CREST, Japan Science and Technology Agency (JST), Tokyo 102-0076, Japan
Corresponding Author: Das, B.P.; Department of Communications and Computer Engineering, Kyoto UniversityJapan; email: bishnu.iisc@gmail.com
Appears in Collections:Journal Publications [ECE]

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