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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/7972
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dc.contributor.authorBarthwal A.-
dc.contributor.authorRawat, Karun-
dc.contributor.authorKoul S.K.-
dc.date.accessioned2020-10-09T05:07:21Z-
dc.date.available2020-10-09T05:07:21Z-
dc.date.issued2018-
dc.identifier.citationIEEE Transactions on Microwave Theory and Techniques (2018), 66(2): 1024-1033-
dc.identifier.issn189480-
dc.identifier.urihttps://doi.org/10.1109/TMTT.2017.2751044-
dc.identifier.urihttp://repository.iitr.ac.in/handle/123456789/7972-
dc.description.abstractThis paper presents a design strategy to enhance the bandwidth of three-stage Doherty power amplifier (DPA) with operation upto 12-dB back-off. Based on the proposed strategy, a broadband 48-W DPA is designed and implemented using packaged CREE GaN transistors. The measured drain efficiency of 50%-61.8% at 12-dB back-off and 51.9%-66.2% at 6-dB back-off is obtained over the frequency range of 600-900 MHz. Over this 300-MHz band, the drain efficiency is between 51.1% and 78% at saturation. This corresponds to 40% fractional bandwidth. The three-stage DPA is also linearized with a three carrier 15-MHz WCDMA signal with a PAPR of 10.6 dB at various frequencies within operating band and shows the output signal qualifies spectral mask specifications. © 2017 IEEE.-
dc.language.isoen_US-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.relation.ispartofIEEE Transactions on Microwave Theory and Techniques-
dc.subjectBroadband-
dc.subjectDoherty power amplifier (DPA)-
dc.subjectefficiency enhancement-
dc.subjectGaN-
dc.subjectload modulation-
dc.subjectthree stage-
dc.titleA Design Strategy for Bandwidth Enhancement in Three-Stage Doherty Power Amplifier with Extended Dynamic Range-
dc.typeArticle-
dc.scopusid57025003000-
dc.scopusid57000644800-
dc.scopusid55849312100-
dc.affiliationBarthwal, A., Centre for Applied Research in Electronics, Delhi, 110016, India-
dc.affiliationRawat, K., Indian Institute of Technology Delhi, Delhi, 110016, India, Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India-
dc.affiliationKoul, S.K., Centre for Applied Research in Electronics, Delhi, 110016, India-
dc.description.fundingManuscript received June 26, 2017; accepted August 25, 2017. Date of publication September 21, 2017; date of current version February 5, 2018. This work was supported by the Department of Science and Technology, Government of India Extra Mural under Grant SB/S3/EECE/047/2014. (Corresponding author: Ayushi Barthwal.) A. Barthwal and S. K. Koul are with the Centre for Applied Research in Electronics, IIT Delhi, Delhi 110016, India (e-mail: barthwal.ayushi1988@gmail.com; shiban_koul@hotmail.com). She was a Student Research Assistant under the GATE Fellowship of Ministry of Human Resource, Government of India. She was an Assistant Pro-fessor with Galgotias University, Greater Noida, India. Her current research interests include microwave active circuit design and advanced power amplifier architectures for upcoming high data-rate communication.-
dc.description.correspondingauthorBarthwal, A.; Centre for Applied Research in ElectronicsIndia; email: barthwal.ayushi1988@gmail.com-
Appears in Collections:Journal Publications [ECE]

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