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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/7969
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dc.contributor.authorShankar R.-
dc.contributor.authorKaushal G.-
dc.contributor.authorMaheshwaram S.-
dc.contributor.authorDasgupta, Sudeb-
dc.contributor.authorManhas, Sanjeev Kumar-
dc.date.accessioned2020-10-09T05:07:21Z-
dc.date.available2020-10-09T05:07:21Z-
dc.date.issued2014-
dc.identifier.citationIEEE Transactions on Device and Materials Reliability (2014), 14(2): 689-697-
dc.identifier.issn15304388-
dc.identifier.urihttps://doi.org/10.1109/TDMR.2014.2310292-
dc.identifier.urihttp://repository.iitr.ac.in/handle/123456789/7969-
dc.description.abstractThe reliability of multigate metal-oxide-semiconductor (MOS) devices is an important issue for novel nanoscale complementary MOS (CMOS) technologies. We present an analytic degradation model of double-gate (DG) and gate-all-around (GAA) MOS field-effect transistors (MOSFETs) in the presence of localized interface charge. Furthermore, we consider the effect of channel mobile charge carriers that significantly enhances the accuracy of our model. In our model, an accurate definition of threshold voltage in terms of minimum channel carrier density is used. The proposed model accurately depicts the effect of hot-carrier-induced degradation (HCD) on the surface potential, threshold voltage, and subthreshold swing. The results show a good agreement with the technology computer-aided design (TCAD) SENTAURUS device simulator over a wide range of device parameters. The modeling results show that the HCD effect become more dominant for scaled-down DG/GAA MOSFET devices. A comparative HCD degradation analysis carried for DG and GAA MOSFETs to understand their reliability limits show that GAA has greater immunity to HCD than DG MOSFET. This highlights model accuracy and provides crucial insights for HCD-tolerant multigate MOSFET design. © 2001-2011 IEEE.-
dc.language.isoen_US-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.relation.ispartofIEEE Transactions on Device and Materials Reliability-
dc.subjectlocalized interface trap charge-
dc.subjectMulti-gate MOSFETs-
dc.subjectsurface potential-
dc.subjectthreshold voltage and subthreshold slope degradation-
dc.titleA degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers-
dc.typeArticle-
dc.scopusid57196611221-
dc.scopusid24178210100-
dc.scopusid42161683700-
dc.scopusid57191737302-
dc.scopusid6602269066-
dc.affiliationShankar, R., Centre of Nanotechnology, Indian Institute of Technology Roorkee, Roorkee 247667, India-
dc.affiliationKaushal, G., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India-
dc.affiliationMaheshwaram, S., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India-
dc.affiliationDasgupta, S., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India-
dc.affiliationManhas, S.K., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India-
Appears in Collections:Journal Publications [ECE]

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