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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/7465
Title: Integrated phase-locking scheme for SDFT-based harmonic analysis of periodic signals
Authors: Sumathi, Parasuraman
Janakiraman P.A.
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs
Abstract: The sliding discrete Fourier transform splits periodic signals into selected harmonic components, as on-line time functions. Ordinarily, the sampling frequency is equal to the product of the nominal signal frequency and the window width N. However, when the signal frequency drifts, to avoid the phase and magnitude errors, the sampling frequency can be adaptively adjusted using the phase-error itself. An integrated phase-locked loop scheme and its parameters like hold-in, pull-in ranges, lock time, steady-state errors are presented in this brief. © 2007 IEEE.
Citation: IEEE Transactions on Circuits and Systems II: Express Briefs (2008), 55(1): 51-55
URI: https://doi.org/10.1109/TCSII.2007.907854
http://repository.iitr.ac.in/handle/123456789/7465
Issue Date: 2008
Keywords: Frequency drift
Harmonic analysis
Phase error
Phase-locked loop (PLL)
Sliding discrete Fourier transform (SDFT)
ISSN: 15497747
Author Scopus IDs: 56998549500
6603751551
Author Affiliations: Sumathi, P., Electrical Engineering, Indian Institute of Technology - Madras (IIT-Madras), Chennai 600036, India
Janakiraman, P.A., Electrical Engineering, Indian Institute of Technology - Madras (IIT-Madras), Chennai 600036, India
Corresponding Author: Sumathi, P.; Electrical Engineering, Indian Institute of Technology - Madras (IIT-Madras), Chennai 600036, India; email: sumichan04@yahoo.co.in
Appears in Collections:Journal Publications [EE]

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