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Title: FPGA implementation of an amplitude-modulated continuous-wave ultrasonic ranger using restructured phase-locking scheme
Authors: Sumathi, Parasuraman
Janakiraman P.A.
Published in: VLSI Design
Abstract: An accurate ultrasonic range finder employing Sliding Discrete Fourier Transform (SDFT) based restructured phase-locked loop (RPLL), which is an improved version of the recently proposed integrated phase-locking scheme (IPLL), has been expounded. This range finder principally utilizes amplitude-modulated ultrasonic waves assisted by an infrared (IR) pilot signal. The phase shift between the envelope of the reference IR pilot signal and that of the received ultrasonic signal is proportional to the range. The extracted envelopes are filtered by SDFT without introducing any additional phase shift. A new RPLL is described in which the phase error is driven to zero using the quadrature signal derived from the SDFT. Further, the quadrature signal is reinforced by another cosine signal derived from a lookup table (LUT). The pulse frequency of the numerically controlled oscillator (NCO) is extremely accurate, enabling fine tuning of the SDFT and RPLL also improves the lock time for the 50Hz input signal to 0.04s. The percentage phase error for the range 0.6m to 6m is about 0.2. The VHDL codes generated for the various signal processing steps were downloaded into a Cyclone FPGA chip around which the ultrasonic ranger had been built. © 2010 P. Sumathi and P. A. Janakiraman.
Citation: VLSI Design (2010), 2010(): -
Issue Date: 2010
ISSN: 1065514X
Author Scopus IDs: 56998549500
Author Affiliations: Sumathi, P., DA-IICT, Department of Information and Communication Technology, Gandhinagar, Gujarat 382007, India
Janakiraman, P.A., Indian Institute of Technology Madras, Department of Electrical Engineering, Chennai 600036, India
Corresponding Author: Sumathi, P.; DA-IICT, Department of Information and Communication Technology, Gandhinagar, Gujarat 382007, India; email:
Appears in Collections:Journal Publications [EE]

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