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Title: A power-line interference canceler based on sliding DFT phase locking scheme for ECG signals
Authors: Mishra S.
Das D.
Kumar R.
Sumathi, Parasuraman
Published in: IEEE Transactions on Instrumentation and Measurement
Abstract: A power-line interference (PLI) removal method is proposed based on a previously published sliding discrete Fourier transform (SDFT) phase locking scheme (PLL), which extracts the nonstationary sinusoids from the electrocardiogram (ECG) signal. The proposed PLI canceler consists of SDFT PLL as a vital element, which can track the variation in center frequency of the PLI either 50 or 60 Hz. The PLI canceler involves the adaptive sampling frequency control in which the sampling frequency of SDFT filter is adaptively adjusted according to the center frequency variation of the interference. Since the in-phase and quadrature components of SDFT filter can provide instantaneous sinusoidal and cosinusoidal interference signals, the SDFT PLL is capable of tracking amplitude, phase, and frequency of the interference. Additional resonators of different bin indices are augmented with SDFT PLL to handle the dominant odd harmonics of PLI. Furthermore, the SDFT PLL is cascaded with another SDFT bin to eliminate the baseline wander present in the real-time ECG signal. The adaptive PLI canceler based on SDFT PLL offers the tracking capability of variant PLI, attenuation of 40 dB, less acquisition time of 0.2 s for a variant PLI of ±5 Hz, removal of dominant odd harmonics, and baseline wander with expense of sampling frequency. Experimental results prove the efficacy of the proposed method in nonstationary sinusoidal interference extraction. Experimental investigation on SDFT PLL using field programmable gate array demonstrates the feasibility of digital implementation of the proposed algorithm. © 2014 IEEE.
Citation: IEEE Transactions on Instrumentation and Measurement (2015), 64(1): 132-142
Issue Date: 2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Adaptive filters
discrete Fourier transform (DFT)
field programmable gate arrays (FPGAs)
interference cancelation
phase locked loop
ISSN: 189456
Author Scopus IDs: 56289143500
Author Affiliations: Mishra, S., Department of Electronics and Communication Engineering, Graphic Era Hill University, Bhimtal, 247667, India
Das, D., Department of Electrical Engineering, IIT Roorkee, Roorkee, 247667, India
Kumar, R., Department of Earthquake Engineering, IIT Roorkee, Roorkee, 247667, India
Sumathi, P., Department of Electrical Engineering, IIT Roorkee, Roorkee, 247667, India
Appears in Collections:Journal Publications [EE]

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