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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/6977
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dc.contributor.authorJain R.-
dc.contributor.authorSiddiqui A.S.-
dc.contributor.authorJamil M.-
dc.contributor.authorGupta, Chandra Prakash-
dc.contributor.authorPreeti-
dc.date.accessioned2020-10-09T04:42:04Z-
dc.date.available2020-10-09T04:42:04Z-
dc.date.issued2013-
dc.identifier.citationInternational Journal of Systems Assurance Engineering and Management (2013), 4(2): 129-137-
dc.identifier.issn9756809-
dc.identifier.urihttps://doi.org/10.1007/s13198-013-0163-8-
dc.identifier.urihttp://repository.iitr.ac.in/handle/123456789/6977-
dc.description.abstractThis research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. © 2013 The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden.-
dc.language.isoen_US-
dc.relation.ispartofInternational Journal of Systems Assurance Engineering and Management-
dc.subjectFACTS-
dc.subjectFrequency locked loops-
dc.subjectPhase locked loop-
dc.subjectSynchronisation-
dc.subjectThyristor pulse-
dc.titleA novel approach for phase locked loop modelling using MATLAB-
dc.typeArticle-
dc.scopusid57191853623-
dc.scopusid55184930700-
dc.scopusid57191203774-
dc.scopusid7202352469-
dc.scopusid56677553700-
dc.affiliationJain, R., YMCA University of Science and Technology, Faridabad, India-
dc.affiliationSiddiqui, A.S., Electrical Engineering Department, Faculty of Engineering and Technology, JMI, New Delhi, India-
dc.affiliationJamil, M., Electrical Engineering Department, Faculty of Engineering and Technology, JMI, New Delhi, India-
dc.affiliationGupta, C.P., Electrical Engineering Department, IIT Roorkee, Roorkee, India-
dc.affiliationPreeti, YMCA University of Science and Technology, Faridabad, India-
dc.description.correspondingauthorPreeti; YMCA University of Science and Technology, Faridabad, India; email: preeti200726@gmail.com-
Appears in Collections:Journal Publications [EE]

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