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dc.contributor.authorPadhy S.-
dc.contributor.authorKumar V.-
dc.contributor.authorSingh U.P.-
dc.identifier.citationJournal of Materials Science: Materials in Electronics (2019), 30(2): 1100-1108-
dc.description.abstractIn the present work, the Copper Zinc Tin Sulfur Selenium (CZTSSe) absorber layer powder was prepared by solid state reaction process using ball mill machine and subsequently the paste was prepared. The paste was deposited using doctor blade method. The deposited films were annealed via two-step and three-step annealing method. For two-step annealing, in the first step the films were first ramped to 250 °C for 10 min and in the second step the temperature was ramped to 500 °C with three different hold times (5,10 and 20 min). Similarly, for the three-step process, samples were first ramped to temperature of 250 °C for 10 min, followed by an intermediate annealing step of 300 °C (10 min) and in the final step the temperature was ramped to 500 °C with two different hold times (5 and 10 min). The goal of the present work is to investigate the effect of annealing through two-step and three-step temperature profile on the CZTSSe absorber layer properties. The films were characterized using XRD (for phase analysis), SEM (for surface morphology), EDXRF (for composition analysis), and Hall Measurement (for electrical properties). It is found that the annealing hold time at higher temperature strongly influences the formation of CZTSSe grain growth, morphology and the electrical properties. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.-
dc.publisherSpringer New York LLC-
dc.relation.ispartofJournal of Materials Science: Materials in Electronics-
dc.titleCZTSSe absorber layer formation and impact of annealing process on its properties-
dc.affiliationPadhy, S., School of Electronics Engineering, KIIT (DU), Bhubaneswar, Odisha 751024, India-
dc.affiliationKumar, V., School of Electronics Engineering, KIIT (DU), Bhubaneswar, Odisha 751024, India-
dc.affiliationSingh, U.P., School of Electronics Engineering, KIIT (DU), Bhubaneswar, Odisha 751024, India-
dc.description.fundingAcknowledgements Financial support by MNRE, New Delhi (31/13/2013-14/PVSE R&D) and DST New Delhi (DST/TMD/CER/ C167(G)).The authors are thankful to Prof R K Singh IIT,BHU for Raman Measurements.-
dc.description.correspondingauthorSingh, U.P.; School of Electronics Engineering, KIIT (DU)India; email:
Appears in Collections:Journal Publications [CY]

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