Skip navigation
Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/27586
Title: Analytical potential distribution model for underlap double gate MOSFETs with 3T-4T and symmetric-asymmetric options for subthreshold operation: A conformal mapping approach
Authors: Vaddi R.
Dasgupta, Sudeb
Agarwal R.P.
Published in: Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010
Abstract: We propose a new analytical model to compute the potential distribution in gate overlap and underlap regions of a 3T- 4T double gate MOSFET valid for symmetric, asymmetric options for operation in the subthreshold condition. Conformai mapping technique has been applied for modeling fringing electric field in the underlap regions. The proposed model has been verified against reported models and a good agreement is found thus proving the accuracy of the proposed model. It has been observed that increasing the gate underlap region has significant effect on reducing short channel effects. The existing DGMOSFET potential models for subthreshold operation does not cover all 3T, 4T, asymmetric gate oxide thickness, asymmetric gate work functions and underlap region, which have been considered while model development. The developed model can be used for developing subthreshold current and slope models for underlap DGMOSFET with arbitrary gate biasing, gate insulator thickness and work functions. These models will simplify analyzing nano scale subthreshold logic circuits and system development of energy constrained applications such as RFID, wireless micro sensors and biomedical applications.
Citation: Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - Technical Proceedings of the 2010 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2010 (2010), 2: 697-700
URI: http://repository.iitr.ac.in/handle/123456789/27586
Issue Date: 2010
Keywords: Analytical subthreshold potential model
Asymmetric double gate
Back gate effects
Conformai mapping
Gate underlap
Independent double gate
Symmetric double gate
Tied double gate
ISBN: 9781439834022
Author Scopus IDs: 26538319600
57191737302
7402481365
Author Affiliations: Vaddi, R., Micro Electronics and VLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee, Roorkee - 247667, Uttarakhand, India
Dasgupta, S., Micro Electronics and VLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee, Roorkee - 247667, Uttarakhand, India
Agarwal, R.P., Micro Electronics and VLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee, Roorkee - 247667, Uttarakhand, India
Funding Details: 
Corresponding Author: Vaddi, R.; Micro Electronics and VLSI Group, , Roorkee - 247667, Uttarakhand, India; email: ramesdec@iitr.ernet.in
Appears in Collections:Conference Publications [ECE]

Files in This Item:
There are no files associated with this item.
Show full item record


Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.