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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/27573
Title: Performance analysis of dual-k spacer at source side for underlap FinFETs
Authors: Pal P.K.
Singh P.
Kaushik B.K.
Anand B.
Dasgupta, Sudeb
Published in: 2012 Annual IEEE India Conference, INDICON 2012
2012 Annual IEEE India Conference, INDICON 2012
Abstract: This paper proposes an overall improvement in performance of Gate-Source/Drain underlap FinFET structure by introducing the concept of dual-k spacer between gate and source. By optimizing the underlap length, we demonstrate the sensitivity of dual-k spacer width. We analyze that the variation in width of high-k presents a noticeable improvements in On-Off current ratio (Ion/Ioff). The proposed structure is verified by TCAD simulations of underlap FinFET device with varying device physical parameters such as spacer width, spacer material etc. and optimizes the width of the high-k and low-k spacer. The proposed device architecture enhances gate control over channel and can be used to design low power digital circuits. © 2012 IEEE.
Citation: 2012 Annual IEEE India Conference, INDICON 2012 (2012): 915-919
URI: https://doi.org/10.1109/INDCON.2012.6420747
http://repository.iitr.ac.in/handle/123456789/27573
Issue Date: 2012
Keywords: double gate devices
dual-k spacers
fringe field
parasitic capacitance
short channel effects
underlap FinFET
ISBN: 9781467322720
Author Scopus IDs: 55602418800
57195147305
57021830600
56247640700
57191737302
Author Affiliations: Pal, P.K., Microelectronics AndVLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, India
Singh, P., Microelectronics AndVLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, India
Kaushik, B.K., Microelectronics AndVLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, India
Anand, B., Microelectronics AndVLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, India
Dasgupta, S., Microelectronics AndVLSI Group, Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, India
Funding Details: 
Corresponding Author: Pal, P.K.; Microelectronics AndVLSI Group, , Roorkee, India; email: pankajpal86@gmail.com
Appears in Collections:Conference Publications [ECE]

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