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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/27558
Title: Reduced Gate Capacitance of Dual Metal Double Gate over Single Metal Double Gate Tunnel FET: A Comparative Study
Authors: Gupta D.
Bagga N.
Dasgupta, Sudeb
Published in: Proc. IEEE Conference on Emerging Devices and Smart Systems, ICEDSS 2018
2018 IEEE Conference on Emerging Devices and Smart Systems, ICEDSS 2018
Abstract: The impact of Dual Metal work function over the Single Metal on the capacitance of the double gate Tunnel FET is explored in this paper. We have comparatively studied the capacitance and the transfer characteristics of Single Metal Double Gate (SMDG) and Dual Metal Double Gate (DMDG) Tunnel FET. In DMDG TFET we have found reduced gate capacitance (C gg ) due to the presence of metal of higher function near the drain. Since the contribution of C gd in the C gg is more as compared to C gs , miller capacitance reduces in DMDG TFETs. © 2018 IEEE.
Citation: Proc. IEEE Conference on Emerging Devices and Smart Systems, ICEDSS 2018 (2018): 110-112
URI: https://doi.org/10.1109/ICEDSS.2018.8544366
http://repository.iitr.ac.in/handle/123456789/27558
Issue Date: 2018
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Capacitance
Double Metal Gate (DMG) TFETs
Single Metal Gate (SMG) TFETs
Subthreshold slope
TFETs
ISBN: 9781538634790
Author Scopus IDs: 57205438424
56669683700
57191737302
Author Affiliations: Gupta, D., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India
Bagga, N., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India
Dasgupta, S., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India
Funding Details: 
Appears in Collections:Conference Publications [ECE]

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