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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/27426
Title: Vertical nanowire FET based standard cell design employing Verilog-A compact model for higher performance
Authors: Maheshwaram S.
Prakash O.
Sharma M.
Anand, Bulusu
Manhas S.
Kaushik B.K.
Dasgupta S.
Singh V.
Published in: Communications in Computer and Information Science
21st International Symposium on VLSI Design and Test, VDAT 2017
Abstract: In sub 10nm technology node, vertical silicon nanowire (VNW) FET device has become a promising substitute due to its better gate controllability, short channel immunity, high ION/IOFF ratio and CMOS compatibility. This paper presents, a standard cell library using physics based Verilog-A compact model for 10nm vertical SiNW FET device. A unified compact model included all the nanoscale effects (e.g. short channel effects, mobility degradation, velocity saturations etc.) as well as the parasitic capacitance and resistance model, which are highly dominant in lower technology nodes. The compact model is well matched with TCAD simulation data at 10nm VNW FET device level. The cell library builds comprises of INVERTER, NAND, NOR and Ex-OR gate cells. Further, we compared the 10nm VNW FET based standard cell performance to 45nm bulk CMOS based standard cell library. It is found that the VNWFET based cells library design have an advantage of delay by~4X and power consumption by~14X against the 45nm CMOS technology. © Springer Nature Singapore Pte Ltd 2017.
Citation: Communications in Computer and Information Science (2017), 711: 239-248
URI: https://doi.org/10.1007/978-981-10-7470-7_24
http://repository.iitr.ac.in/handle/123456789/27426
Issue Date: 2017
Publisher: Springer Verlag
Keywords: Cell library
Parasitic capacitance and parasitic resistance model
Verilog-A compact model and vertical nanowire FET
ISBN: 9789811074691
ISSN: 18650929
Author Scopus IDs: 42161683700
57210722800
57201968490
56247640700
6602269066
Author Affiliations: Maheshwaram, S., Marri Laxman Reddy Institute of Technology and Management, Hyderabad, India
Prakash, O., Indian Institute of Technology Roorkee, Roorkee, 247667, India
Sharma, M., Xilinx Hyderabad, Hyderabad, India
Bulusu, A., Indian Institute of Technology Roorkee, Roorkee, 247667, India
Manhas, S., Indian Institute of Technology Roorkee, Roorkee, 247667, India
Funding Details: We Dr. Satish Maheshwaram and Mr. Mohit Sharma, would like to thank our co-author Mr. Om Prakash and our supervisors Dr. Anand Bulusu, Dr. Sanjeev Manhas who have redone the work (after our graduation) on standard cell library delay and power analysis at Indian Institute of Technology Roorkee to make this a better research work. Indian Institute of Technology Roorkee, IITR
Corresponding Author: Maheshwaram, S.; Marri Laxman Reddy Institute of Technology and ManagementIndia; email: satishm@mlritm.ac.in
Appears in Collections:Conference Publications [ECE]

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