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Title: Compact modeling of a generic double-gate MOSFET with gate-S/D underlap for subthreshold operation
Authors: Vaddi R.
Agarwal R.P.
Dasgupta, Sudeb
Published in: IEEE Transactions on Electron Devices
Abstract: In this brief, a new analytical model to compute the potential distribution in gate overlap and underlap regions of a generic double-gate (DG) MOSFET (valid for asymmetric features in front- and back-gate insulator thicknesses, gate bias, and gate work functions) for operation in the subthreshold condition is proposed. A closed form solution to 2-D Poisson's equation is obtained with approximation of parabolic potential function along vertical direction of the device. Conformal mapping technique is applied for modeling fringe electric field in the underlap regions. The proposed potential model is extended in deriving important device parameters such as threshold voltage, threshold voltage rolloff, DIBL, subthreshold swing, etc. Model predictions demonstrate that significant improvement in subthreshold operation can be achieved with 4T asymmetric underlap DG MOSFETs in comparison to 3T symmetric nonunderlap DG MOSFETs. © 2012 IEEE.
Citation: IEEE Transactions on Electron Devices, 59(10): 2846-2849
Issue Date: 2012
Keywords: Analytical subthreshold model
asymmetric double-gate (DG) (ADG) MOSFET
compact modeling
fringe field modeling
gate underlap
independent (4T) DG MOSFET
ISSN: 189383
Author Scopus IDs: 26538319600
Author Affiliations: Vaddi, R., Department of ECE, Padmasri Dr. B.V. Raju Institute of Technology, Hyderabad 500082, India
Agarwal, R.P., Shobhit University, Meerut 250110, India
Dasgupta, S., Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee, Roorkee 247667, India
Funding Details: 
Corresponding Author: Vaddi, R.; Department of ECE, , Hyderabad 500082, India; email:
Appears in Collections:Journal Publications [ECE]

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