Design and analysis of analog performance of dual-k spacer underlap N/P-FinFET at 12 nm gate length

Abstract

Among the multigate structures, FinFET is emerging as a promising candidate due to its better gate electrostatic control and ease of manufacturability. However, loss of gate electrostatic integrity (EI) is still observed in FinFET while it is scaled down to nano-scale regime, resulting in deterioration of analog performance. Most importantly, precise dimensional requirements and process challenges are major hurdles at nano-scale regime resulting in device-to-device variability. Nevertheless, efficient use of gate sidewall fringing fields, by use of an inner high-k spacer, can restore the loss of gate control. In this paper, we observe that, due to excellent gate EI, the analog performance of dual-k spacer-based underlap N/P-FinFET is better than the conventional low-k N/P-FinFET. Simulation results at 12 nm gate length reveal that dual-k N/P-FinFETs are capable of targeting high-gain, low-power, and moderate frequency of operation even with lower aspect ratio (fin height/fin width) and higher fin width, oxide thickness, and lateral straggle. In addition, the figures of merit of dual-k N/P-FinFETs are less variable to major parametric variations such as fin width and oxide thickness. These attractive features prove to be handy in designing circuitry for low-power battery-operated portable gadgets. © 2013 IEEE.