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dc.contributor.authorNandi A.-
dc.contributor.authorSaxena A.K.-
dc.contributor.authorDasgupta, Sudeb-
dc.identifier.citationMicroelectronics Journal, 55: 19-25-
dc.description.abstractAs the gate lengths of FinFETs are scaled into nano meter regime, spatial variations in oxide thickness (Tox) and junction depth (Xj) of source/drain (S/D) doping profile will largely decide the performance of digital and analog circuits that can fall below or above the desired value. Of particular importance is operational transconductance amplifier (OTA), where the crucial analog figures of merit (FOM) such as differential mode gain (ADM), common mode gain (ACM) and common mode rejection ratio (CMRR) decide the suitability of its use at nanometer regime. In the present work, we have studied the analog performance variation of low-k (dual-k) underlap FinFET based single stage OTA with spatial variation in Tox and Xj of S/D profile. Enhanced and variation less threshold voltage and mobility of dual-k underlap FinFET due to of better screening of longitudinal field and pronounced volume inversion effect, are studied in detail. It is observed that at 16 nm gate length the best case ADM, ACM and CMRR of low-k (dual-k) FinFET based OTA are 34.2 dB (42.3 dB), 26 dB m (18 dB m), 68.2 dB (84.2 dB) respectively. Subsequently, the spatial variation of Tox and Xj leads to worst case change in ADM and ACM of low-k (dual-k) FinFET based OTA by −6.8 dB (−2.2 dB) and +28.2 dB m (+31.3 dB m) respectively. The negligible deterioration in ACM of dual-k FinFET OTA transforms into CMRR improvements of 37% at this worst case condition as compared to CMRR of low-k FinFET OTA. Furthermore, with gate length scaling, the FOM and their percentage change with Tox and Xj of dual-k FinFET OTA are much better than that of low-k FinFET OTA. © 2016 Elsevier Ltd-
dc.publisherElsevier Ltd-
dc.relation.ispartofMicroelectronics Journal-
dc.subjectCommon mode gain (ACM)-
dc.subjectCommon mode rejection ratio (CMRR)-
dc.subjectDifferential mode gain (ADM)-
dc.subjectElectrostatic integrity (EI)-
dc.titleOxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET-
dc.affiliationNandi, A., Department of Electronics and Communication Engineering, National Institute of Technology Kurukshetra, Haryana, Kurukshetra 136119, India-
dc.affiliationSaxena, A.K., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, Uttarakhand 247667, India-
dc.affiliationDasgupta, S., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, Uttarakhand 247667, India-
dc.description.correspondingauthorNandi, A.; Department of Electronics and Communication Engineering, India; email:
Appears in Collections:Journal Publications [ECE]

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