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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/25886
Title: Analytical Modeling of Gate-Stack DG-MOSFET in Subthreshold Regime by Green's Function Approach
Authors: Nandi A.
Pandey N.
Dasgupta, Sudeb
Published in: IEEE Transactions on Electron Devices
Abstract: An accurate analytical model of the gate-stack symmetric double-gate (DG) MOSFET using Green's function approach is developed in this brief. An exact analytical solution to 2-D Poisson's equation is derived in the subthreshold regime of operation, considering 2-D mixed boundary conditions and multizone techniques. It is observed that the Green's function approach of solving 2-D Poisson's equation in both oxides (tox1 and tox2) and silicon region can accurately predict channel potential and subthreshold current (Isub) of gate-stack DG-MOSFET. We further extend our model to mitigate the fringe-induced barrier lowering (FIBL) effect in the gate-stack device, by optimizing the interfacial layer thickness. It is observed that selection of interfacial SiO2 layer as ∼0.75 times of equivalent oxide thickness is necessary to completely mitigate the FIBL effect of SiO2-HfO2-based gate-stack DG-MOSFET. © 2018 IEEE.
Citation: IEEE Transactions on Electron Devices, 65(10): 4724-4728
URI: https://doi.org/10.1109/TED.2018.2862872
http://repository.iitr.ac.in/handle/123456789/25886
Issue Date: 2018
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Fringe-induced barrier lowering (FIBL)
Green's function approach
multizone techniques
ISSN: 189383
Author Scopus IDs: 55260064900
57194501995
57191737302
Author Affiliations: Nandi, A., Department of Electronics and Communication Engineering, National Institute of Technology Kurukshetra, Kurukshetra, 136119, India
Pandey, N., Department of Electronics and Communication Engineering, National Institute of Technology Kurukshetra, Kurukshetra, 136119, India
Dasgupta, S., Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, 247667, India
Funding Details: 
Corresponding Author: Nandi, A.; Department of Electronics and Communication Engineering, India; email: ashutosh.chl@gmail.com
Appears in Collections:Journal Publications [ECE]

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