Vlsi implementation of adiabatic logic-based 4×4 multiplier for low power applications

Abstract

Very large scale integrated circuits are the backbone of modern semiconductor industry to fulfill the need of high speed and low power electronic systems. High speed data processors consist of arithmetic logic units and multiplier is a major part of these logic units. In this paper, a high speed low power 4 × 4 multiplier has been implemented using an adiabatic logic-based full adder. The proposed design of multiplier consumes a power of 0.018 µW as compared to 1.78 µW double pass transistor with asynchronous adiabatic logic-based multiplier reported in literature with a frequency of 100 MHz. The performance of proposed design has been verified at varying voltage supply and temperature conditions. The simulated results show that the proposed architecture of multiplier is a better option for low power VLSI circuits. © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd 2020.