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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22508
Title: A physical insight into variation aware minimum v DDfor deep subthreshold operation of FinFET
Authors: Yadav S.
Chauhan N.
Tyagi S.
Sharma A.
Banchhor S.
Joshi R.
Pratap R.
Anand, Bulusu
Published in: Semiconductor Science and Technology
Abstract: Several ultra-low power applications, that do not require high performance, can benefit from operation at the lowest possible supply voltage. Scaling of supply voltage is an effective method to reduce the energy consumption in digital circuits. The fundamental limit for supply voltage has been established as 36 mV for planar complementary metal oxide semiconductor (CMOS) circuits based on Shannon's channel capacity theorem. Owing to its near ideal sub-threshold characteristics, fin field effect transistor (FinFET) devices are a better fit for ultra-low voltage applications than planar devices. In this work, the fundamental limit on supply voltage for FinFET based logic circuits has been established for the first time. This theoretical limit is found to be significantly lower than the limit for planar CMOS circuits. The effect of variation of temperature and device design parameters on this fundamental limit is also explored. The analysis is extended to other logic gates such as NAND gate. Since the operation of a FinFET device in the ultra-low voltage domain is quite different from its planar counterpart, a novel physics based, semi-empirical current equation valid for supply voltage below 100 mV has been proposed for a FinFET device to calculate this fundamental limit. Such a current model is of great importance to a circuit designer because of the ease it offers for the back of the envelope calculations. The logic gates operating in this regime are then analyzed using this proposed model. © 2021 IOP Publishing Ltd.
Citation: Semiconductor Science and Technology, 36(12)
URI: https://doi.org/10.1088/1361-6641/ac2d0f
http://repository.iitr.ac.in/handle/123456789/22508
Issue Date: 2021
Publisher: IOP Publishing Ltd
Keywords: FinFET extension length
fundamental limits
inverter
minimum voltage supply
sub-threshold operation
temperature variability
ultra-low voltage FinFET logic
ISSN: 2681242
Author Scopus IDs: 57205425622
57209393334
57202332109
55482800900
56879230200
57329599600
57202623000
56247640700
Author Affiliations: Yadav, S., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India, Department of Electronics Engineering, National Institute of Technology, Uttarakhand, Srinagar, 246174, India
Chauhan, N., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India, Department of Electronics Engineering, National Institute of Technology, Uttarakhand, Srinagar, 246174, India
Tyagi, S., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India
Sharma, A., University of Minnesota, Minneapolis, MN, United States
Banchhor, S., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India
Joshi, R., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India
Pratap, R., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India
Bulusu, A., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India
Corresponding Author: Yadav, S.; Department of Electronics and Communication Engineering, India; email: sarita21992@gmail.com Bulusu, A.; Department of Electronics and Communication Engineering, India; email: anand.bulusu@ece.iitr.ac.in
Appears in Collections:Journal Publications [ECE]

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