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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22476
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dc.contributor.authorKumar R.-
dc.contributor.authorBalasubramanian R.-
dc.contributor.authorKumar Kaushik, Brajesh-
dc.date.accessioned2022-03-21T09:47:24Z-
dc.date.available2022-03-21T09:47:24Z-
dc.date.issued2021-
dc.identifier.citationIEEE Transactions on Intelligent Transportation Systems, 22(10): 6536-6546-
dc.identifier.issn15249050-
dc.identifier.urihttps://doi.org/10.1109/TITS.2020.2993906-
dc.identifier.urihttp://repository.iitr.ac.in/handle/123456789/22476-
dc.description.abstractReal-time video defogging has a huge demand in intelligent transportation, advanced driver assistance systems (ADAS), long-range surveillance, autonomous aerial vehicles and endoscopic surgery. Most of these applications are constrained by stringent frame rate, power and memory budget. Till date, the methods devised for such requirements are very rare. Therefore, this paper proposes an efficient method and very-large-scale integration (VLSI) architecture for resource-constrained embedded system targeting real-time video defogging. The method and architecture are co-designed to achieve high throughput while consuming less resources and power. The architecture is divided into four parts namely, atmospheric light estimation unit, airlight adjustment unit, transmission estimation unit, and pixel restoration unit. The atmospheric light estimation unit employs a 3\times 3 tile based approach that eliminates the requirement of large buffer memory for 15\times 15 support size. The transmission is estimated using dark channel prior and gradient threshold based Gaussian filtering approach. In order to overcome flickering artifacts, an adaptive airlight updating scheme is employed. From the quantitative and qualitative evaluations, it is observed that the proposed method outperforms the existing hardware approaches. Furthermore, the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations of the architecture achieve a high throughput of 200 MPixels/s and 600 MPixels/s, respectively. The ASIC implementation dissipates 9.03 mW power at 200MHz. Moreover, the proposed design does not require any external memory such as dynamic random-access memory (DRAM), thus making it suitable for on-chip processing that can be closely integrated with an image sensor. © 2000-2011 IEEE.-
dc.language.isoen_US-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.relation.ispartofIEEE Transactions on Intelligent Transportation Systems-
dc.subjectDefogging-
dc.subjectdehazing-
dc.subjectflicker reduction-
dc.subjecthardware implementation-
dc.subjectvideo processing-
dc.titleEfficient Method and Architecture for Real-Time Video Defogging-
dc.typeArticle-
dc.scopusid57214462820-
dc.scopusid7103127999-
dc.scopusid57021830600-
dc.affiliationKumar, R., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India-
dc.affiliationBalasubramanian, R., Department of Computer Science and Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India-
dc.affiliationKaushik, B.K., Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, 247667, India-
dc.description.correspondingauthorKaushik, B.K.; Department of Electronics and Communication Engineering, India; email: bkk23fec@iitr.ac.in-
Appears in Collections:Journal Publications [ECE]

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