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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22420
Title: A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell size
Authors: Natarajan S.
Agostinelli M.
Akbar S.
Bost M.
Bowonder A.
Chikarmane V.
Chouksey S.
Dasgupta, Avirup
Fischer K.
Fu Q.
Ghani T.
Giles M.
Govindaraju S.
Grover R.
Han W.
Hanken D.
Haralson E.
Haran M.
Heckscher M.
Heussner R.
Jain P.
James R.
Jhaveri R.
Jin I.
Kam H.
Karl E.
Kenyon C.
Liu M.
Luo Y.
Mehandru R.
Morarka S.
Neiberg L.
Packan P.
Paliwal A.
Parker C.
Patel P.
Patel R.
Pelto C.
Pipes L.
Plekhanov P.
Prince M.
Rajamani S.
Sandford J.
Sell B.
Sivakumar S.
Smith P.
Song B.
Tone K.
Troeger T.
Wiedemer J.
Yang M.
Zhang K.
Published in: Technical Digest - International Electron Devices Meeting, IEDM
2014 60th IEEE International Electron Devices Meeting, IEDM 2014
Abstract: A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing. © 2014 IEEE.
Citation: Technical Digest - International Electron Devices Meeting, IEDM (2015), 2015-February(February): 3.7.1-3.7.3
URI: https://doi.org/10.1109/IEDM.2014.7046976
http://repository.iitr.ac.in/handle/123456789/22420
Issue Date: 2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: FinFET
Fins (heat exchange)
Strained silicon
Doping techniques
Drive currents
High volume manufacturing
HIGH-K metal gates
Logic technology
Patterning layers
Rectangular fins
Self-aligned double patterning
Computer circuits
ISBN: 9.78148E+12
ISSN: 1631918
Author Scopus IDs: 15065730800
55884026600
56742869000
7103267984
24512284100
6602264097
57215269950
56389226300
56742712100
56742671200
6603617245
57119092800
57215278401
7103356177
57220975174
24724144100
57215274404
56742965100
56743180700
8565191600
25923435900
57198191298
57215280053
56146680800
57215286647
15759504700
7103045863
25650255400
57215301062
6701803690
23486209100
6602792307
6603051624
57197544361
57214367187
56408906900
56742640600
6507140175
36950404500
35090534000
57206231760
56742931800
7003517921
6603466179
7006729088
57214269194
54998754900
57198006898
24726332100
24780138300
35194966400
7404450855
Author Affiliations: Natarajan, S., Logic Technology Development, United States
Agostinelli, M., Quality and Reliability Engineering, United States
Akbar, S., Logic Technology Development, United States
Bost, M., Logic Technology Development, United States
Bowonder, A., Logic Technology Development, United States
Chikarmane, V., Logic Technology Development, United States
Chouksey, S., Logic Technology Development, United States
Dasgupta, A., Logic Technology Development, United States
Fischer, K., Logic Technology Development, United States
Fu, Q., Logic Technology Development, United States
Ghani, T., Logic Technology Development, United States
Giles, M., DTS, Intel Corporation, United States
Govindaraju, S., Logic Technology Development, United States
Grover, R., Logic Technology Development, United States
Han, W., Logic Technology Development, United States
Hanken, D., Logic Technology Development, United States
Haralson, E., Logic Technology Development, United States
Haran, M., Logic Technology Development, United States
Heckscher, M., Logic Technology Development, United States
Heussner, R., Logic Technology Development, United States
Jain, P., Logic Technology Development, United States
James, R., Logic Technology Development, United States
Jhaveri, R., Logic Technology Development, United States
Jin, I., Logic Technology Development, United States
Kam, H., Logic Technology Development, United States
Karl, E., Logic Technology Development, United States
Kenyon, C., Logic Technology Development, United States
Liu, M., Logic Technology Development, United States
Luo, Y., Logic Technology Development, United States
Mehandru, R., DTS, Intel Corporation, United States
Morarka, S., DTS, Intel Corporation, United States
Neiberg, L., Logic Technology Development, United States
Packan, P., Logic Technology Development, United States
Paliwal, A., Logic Technology Development, United States
Parker, C., Logic Technology Development, United States
Patel, P., Logic Technology Development, United States
Patel, R., Logic Technology Development, United States
Pelto, C., Logic Technology Development, United States
Pipes, L., Logic Technology Development, United States
Plekhanov, P., Logic Technology Development, United States
Prince, M., Logic Technology Development, United States
Rajamani, S., Logic Technology Development, United States
Sandford, J., Logic Technology Development, United States
Sell, B., Logic Technology Development, United States
Sivakumar, S., Logic Technology Development, United States
Smith, P., Logic Technology Development, United States
Song, B., Logic Technology Development, United States
Tone, K., Logic Technology Development, United States
Troeger, T., Logic Technology Development, United States
Wiedemer, J., Logic Technology Development, United States
Yang, M., Logic Technology Development, United States
Zhang, K., Logic Technology Development, United States
Appears in Collections:Conference Publications [ECE]

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