http://repository.iitr.ac.in/handle/123456789/22417
Title: | BSIM-CMG: Standard FinFET compact model for advanced circuit design |
Authors: | Duarte J.P. Khandelwal S. Medury A. Hu C. Kushwaha P. Agarwal H. Dasgupta, Avirup Chauhan Y.S. Dielacher F. Pribyl W. Hueber G. |
Published in: | European Solid-State Circuits Conference 41st European Solid-State Circuits Conference, ESSCIRC 2015 |
Abstract: | This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes. © 2015 IEEE. |
Citation: | European Solid-State Circuits Conference (2015), 2015-October: 196-201 |
URI: | https://doi.org/10.1109/ESSCIRC.2015.7313862 http://repository.iitr.ac.in/handle/123456789/22417 |
Issue Date: | 2015 |
Publisher: | IEEE Computer Society |
Keywords: | Bias voltage Design Field effect transistors Integrated circuits Quantum theory Reconfigurable hardware Threshold voltage Advanced technology Circuit designs Field penetration Industry standards Physical effects Quantum mechanical confinement Short-channel effect Threshold voltage modulations Integrated circuit manufacture |
ISBN: | 9.78147E+12 |
ISSN: | 19308833 |
Author Scopus IDs: | 56430485900 55625521800 54881050900 35594318600 56149406100 53866052200 56389226300 14029622100 |
Author Affiliations: | Duarte, J.P., Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, United States Khandelwal, S., Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, United States Medury, A., Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, United States Hu, C., Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, United States Kushwaha, P., Nanolab, Dept. of Electrical Engineering, Indian Institute of Technology Kanpur, India Agarwal, H., Nanolab, Dept. of Electrical Engineering, Indian Institute of Technology Kanpur, India Dasgupta, A., Nanolab, Dept. of Electrical Engineering, Indian Institute of Technology Kanpur, India Chauhan, Y.S., Nanolab, Dept. of Electrical Engineering, Indian Institute of Technology Kanpur, India |
Appears in Collections: | Conference Publications [ECE] |
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