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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22403
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dc.contributor.authorChauhan Y.S.-
dc.contributor.authorYadav C.-
dc.contributor.authorDasgupta, Avirup-
dc.contributor.authorRastogi P.-
dc.date.accessioned2022-03-21T09:46:05Z-
dc.date.available2022-03-21T09:46:05Z-
dc.date.issued2019-
dc.identifier.citationICECE 2018 - 10th International Conference on Electrical and Computer Engineering (2019): 1-6-
dc.identifier.isbn9.78154E+12-
dc.identifier.urihttps://doi.org/10.1109/ICECE.2018.8636695-
dc.identifier.urihttp://repository.iitr.ac.in/handle/123456789/22403-
dc.description.abstractIn this paper, we show the impact of channel thickness scaling on material and transistor behavior. we present effect of the strain on energy bandgap in scaled Si and Ge slabs for varying thickness. For lower effective mass III-V channel materials, influence of the lower density of states and contribution of multiple subbands on the gate capacitance and drain current in thin body metal-oxide-semiconductor devices are discussed using the numerical simulation and compact model. We present doping strategy for monolayer MoS2 to increase free charge carrier density to increase drive current in MoS2 based transistors. We also discuss compact modeling approach for 2D transition metal dichalcogenide materials-based transistors for early circuit evaluation. © 2018 IEEE.-
dc.language.isoen_US-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.relation.ispartofICECE 2018 - 10th International Conference on Electrical and Computer Engineering-
dc.relation.ispartof10th International Conference on Electrical and Computer Engineering, ICECE 2018-
dc.subject2D material-
dc.subjectFinFET-
dc.subjectGate-All-Around FET-
dc.subjectGermenium-
dc.subjectIII-V-
dc.subjectNanosheet transistor-
dc.subjectQuantum capacitance-
dc.subjectSilicon-
dc.subjectStrain-
dc.titleAtomistic simulation and compact modeling of atomically thin transistors-
dc.typeConference Paper-
dc.scopusid14029622100-
dc.scopusid55767883400-
dc.scopusid56389226300-
dc.scopusid56463671700-
dc.affiliationChauhan, Y.S., Department of Electrical Engineering, Nanolab, Indian Institute of Technology Kanpur, India-
dc.affiliationYadav, C., IMS Laboratory, University of Bordeaux, Talence Cedex, 33405, France-
dc.affiliationDasgupta, A., Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, United States-
dc.affiliationRastogi, P., Department of Electrical Engineering, Nanolab, Indian Institute of Technology Kanpur, India-
dc.identifier.conferencedetails10th International Conference on Electrical and Computer Engineering, ICECE 2018, 20 - 22, December, 2018-
Appears in Collections:Conference Publications [ECE]

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