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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22403
Title: Atomistic simulation and compact modeling of atomically thin transistors
Authors: Chauhan Y.S.
Yadav C.
Dasgupta, Avirup
Rastogi P.
Published in: ICECE 2018 - 10th International Conference on Electrical and Computer Engineering
10th International Conference on Electrical and Computer Engineering, ICECE 2018
Abstract: In this paper, we show the impact of channel thickness scaling on material and transistor behavior. we present effect of the strain on energy bandgap in scaled Si and Ge slabs for varying thickness. For lower effective mass III-V channel materials, influence of the lower density of states and contribution of multiple subbands on the gate capacitance and drain current in thin body metal-oxide-semiconductor devices are discussed using the numerical simulation and compact model. We present doping strategy for monolayer MoS2 to increase free charge carrier density to increase drive current in MoS2 based transistors. We also discuss compact modeling approach for 2D transition metal dichalcogenide materials-based transistors for early circuit evaluation. © 2018 IEEE.
Citation: ICECE 2018 - 10th International Conference on Electrical and Computer Engineering (2019): 1-6
URI: https://doi.org/10.1109/ICECE.2018.8636695
http://repository.iitr.ac.in/handle/123456789/22403
Issue Date: 2019
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: 2D material
FinFET
Gate-All-Around FET
Germenium
III-V
Nanosheet transistor
Quantum capacitance
Silicon
Strain
ISBN: 9.78154E+12
Author Scopus IDs: 14029622100
55767883400
56389226300
56463671700
Author Affiliations: Chauhan, Y.S., Department of Electrical Engineering, Nanolab, Indian Institute of Technology Kanpur, India
Yadav, C., IMS Laboratory, University of Bordeaux, Talence Cedex, 33405, France
Dasgupta, A., Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, United States
Rastogi, P., Department of Electrical Engineering, Nanolab, Indian Institute of Technology Kanpur, India
Appears in Collections:Conference Publications [ECE]

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