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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22402
Title: Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET
Authors: Kushwaha P.
Agarwal H.
Mishra V.
Dasgupta, Avirup
Lin Y.-K.
Kao M.-Y.
Chauhan Y.S.
Salahuddin S.
Hu C.
Published in: 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Abstract: Lateral nanosheet field-effect-transistor (FET) is now targeting for 3nm CMOS technology node [1], [2]. It is important to see quantization effect at such confined geometry. In this work, we study the geometrical confinement effects in silicon nanosheet. We developed a unified phenomenological model for insulator capacitance (Cins) in rectangular (i.e., Nanosheet) cross-section gate-all-around (GAA) FET to solve the gate charge density accurately. It is observed that multi-subband conduction causes humps in higher order derivatives of charge vs gate voltage characteristics which may affect the performance of analog and RF circuits. © 2019 IEEE.
Citation: 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 (2019)
URI: https://doi.org/10.1109/S3S46989.2019.9320660
http://repository.iitr.ac.in/handle/123456789/22402
Issue Date: 2019
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Capacitance
Microelectronics
Nanosheets
Quantum channel
Confined geometries
Gate charge density
Gate-all-around MOSFET
Geometrical confinement effects
Higher order derivatives
Insulator capacitance
Phenomenological modeling
Quantization effects
MOSFET devices
ISBN: 9.78173E+12
Author Scopus IDs: 56149406100
53866052200
56044135500
56389226300
57188827132
57201524601
14029622100
8544299000
35594318600
Author Affiliations: Kushwaha, P.
Agarwal, H.
Mishra, V.
Dasgupta, A.
Lin, Y.-K.
Kao, M.-Y.
Chauhan, Y.S.
Salahuddin, S.
Hu, C.
Appears in Collections:Conference Publications [ECE]

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