Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits

Abstract

For sub-20-nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, negative bias temperature instability (NBTI) is an important reliability issue and requires an accurate model to predict device and circuit performance. In this paper, we report a well-calibrated predictive and scalable compact Verilog-A-based compact model, integrated with an NBTI model for NW CMOS circuit simulation and design. The stress and recovery NBTI model for an Si NW field-effect transistor is obtained from experimental NW pMOSFETs using a range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar metal-oxide semiconductor field-effect transistors. This is attributed to its cylindrical gate structure, resulting in enhanced 2-D hydrogen diffusion and stress-induced Si/SiO2 traps. This emphasizes the need to evaluate NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: an inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, the interface states generation, inverter delay, and RO frequency degrade rapidly and saturate over the long-term 10-year lifetime. Finally, the design of the SRAM cell employing the multiwire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using the appropriate design configuration. This paper underscores the need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at the device and circuit level. © 2017 IEEE.