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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22361
Title: Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect
Authors: Sahu Y.
Kushwaha P.
Dasgupta, Avirup
Hu C.
Chauhan Y.S.
Published in: IEEE Transactions on Microwave Theory and Techniques
Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases. © 1963-2012 IEEE.
Citation: IEEE Transactions on Microwave Theory and Techniques, 65(7): 2261-2270
URI: https://doi.org/10.1109/TMTT.2017.2666811
http://repository.iitr.ac.in/handle/123456789/22361
Issue Date: 2017
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Compact model
fully depleted silicon on insulator (FDSOI) MOSFET
high-frequency (HF) noise parameters thermal noise
ISSN: 189480
Author Scopus IDs: 57191851575
56149406100
56389226300
35594318600
14029622100
Author Affiliations: Sahu, Y., Nanolab, Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, 208016, India
Kushwaha, P., Nanolab, Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, 208016, India
Dasgupta, A., Nanolab, Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, 208016, India
Hu, C., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Chauhan, Y.S., Nanolab, Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, 208016, India
Funding Details: This work was supported in part by the Semiconductor Research Corporation, in part by the DST Fast Track Scheme for Young Scientist, and in part by the Science and Engineering Research Board. Semiconductor Research Corporation, SRC; Department of Science and Technology, Ministry of Science and Technology, India, डीएसटी; Science and Engineering Research Board, SERB
Appears in Collections:Journal Publications [ECE]

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