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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22356
Title: Proposal for capacitance matching in negative capacitance field-effect transistors
Authors: Agarwal H.
Kushwaha P.
Lin Y.-K.
Kao M.-Y.
Liao Y.-H.
Dasgupta, Avirup
Salahuddin S.
Hu C.
Published in: IEEE Electron Device Letters
Abstract: Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance {C}-{\textsf {fe}} and the underlying MOS transistor {C}-{\textsf {MOS}}. Since both {C}-{\textsf {MOS}} and {C}-{\textsf {fe}} have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of {C}-{\textsf {fe}} The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-Threshold swing as well as lower power supply {V}-{\textsf {dd}} compared with a prototype single-layer negative-capacitance field-effect transistor. © 1980-2012 IEEE.
Citation: IEEE Electron Device Letters, 40(3): 463-466
URI: https://doi.org/10.1109/LED.2019.2891540
http://repository.iitr.ac.in/handle/123456789/22356
Issue Date: 2019
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: capacitance matching
ferroelectric
NCFET
sub 60 mV/decade
ISSN: 7413106
Author Scopus IDs: 53866052200
56149406100
57188827132
57201524601
57191576454
56389226300
8544299000
35594318600
Author Affiliations: Agarwal, H., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Kushwaha, P., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Lin, Y.-K., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Kao, M.-Y., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Liao, Y.-H., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Dasgupta, A., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Salahuddin, S., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Hu, C., Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, United States
Funding Details: Manuscript received December 16, 2018; accepted January 5, 2019. Date of publication January 9, 2019; date of current version March 6, 2019. This work was supported in part by the Berkeley Center for Negative Capacitance Technology and in part by the Berkeley Device Modeling Center. The review of this letter was arranged by Editor K. J. Kuhn. (Corresponding author: Harshit Agarwal.) The authors are with the Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720 USA (e-mail: harshit@berkeley.edu).
Corresponding Author: Agarwal, H.; Department of Electrical Engineering and Computer Science, United States; email: harshit@berkeley.edu
Appears in Collections:Journal Publications [ECE]

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