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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22353
Title: Spacer Engineering in Negative Capacitance FinFETs
Authors: Lin Y.-K.
Agarwal H.
Kao M.-Y.
Zhou J.
Liao Y.-H.
Dasgupta, Avirup
Kushwaha P.
Salahuddin S.
Hu C.
Published in: IEEE Electron Device Letters
Abstract: The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corner spacer improves the inverter propagation delay of the baseline FinFET, the NC-FinFET requires the fin selective spacer with the spacer height up to the ferroelectric thickness for better capacitance matching. When the wire capacitance is 3 times larger than the gate capacitance, the inverter propagation delay of the NC-FinFET with the fin selective spacer can be improved by 8% against the full spacer design. However, with the consideration of process complexity, the air spacer may still be attractive in the NC-FinFET, since it does not suffer from the amplified gate capacitance. © 1980-2012 IEEE.
Citation: IEEE Electron Device Letters, 40(6): 1009-1012
URI: https://doi.org/10.1109/LED.2019.2911104
http://repository.iitr.ac.in/handle/123456789/22353
Issue Date: 2019
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Ferroelectrics
FinFET
negative capacitance
parasitic capacitance
spacer
ISSN: 7413106
Author Scopus IDs: 57188827132
53866052200
57201524601
57193515930
57191576454
56389226300
56149406100
8544299000
35594318600
Author Affiliations: Lin, Y.-K., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Agarwal, H., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Kao, M.-Y., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Zhou, J., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Liao, Y.-H., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Dasgupta, A., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Kushwaha, P., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Salahuddin, S., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Hu, C., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States
Funding Details: Manuscript received April 4, 2019; revised April 9, 2019 and April 10, 2019; accepted April 10, 2019. Date of publication April 15, 2019; date of current version May 23, 2019. This work was supported in part by the Berkeley Device Modeling Center (BDMC) and in part by the Berkeley Center for Negative Capacitance Transistors (BCNCT), University of California at Berkeley, Berkeley, CA, USA. The review of this letter was arranged by Editor S. Hall. (Corresponding author: Yen-Kai Lin.) The authors are with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720 USA (e-mail: yklin@berkeley.edu). University of California Berkeley, UC Berkeley
Corresponding Author: Lin, Y.-K.; Department of Electrical Engineering and Computer Sciences, United States; email: yklin@berkeley.edu
Appears in Collections:Journal Publications [ECE]

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