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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/22351
Title: BSIM compact model of quantum confinement in advanced nanosheet FETs
Authors: Dasgupta, Avirup
Parihar S.S.
Kushwaha P.
Agarwal H.
Kao M.-Y.
Salahuddin S.
Chauhan Y.S.
Hu C.
Published in: IEEE Transactions on Electron Devices
Abstract: We propose a compact model for nanosheet FETs that take the effects of quantum confinement into account. The model captures the nanosheet width and thickness dependence of the electrostatic dimension, density of states, effective mass, subband energies, and threshold voltages and includes them in the charge calculation, resulting in an accurate terminal charge and current characteristics. The model has been implemented using Verilog-A in the BSIM-CMG framework for all simulations. It has been validated with band-structure calculation-based TCAD simulations as well as measured data. We have also highlighted the significance of quantum mechanical effects on analog and RF performance of the device. © 1963-2012 IEEE.
Citation: IEEE Transactions on Electron Devices, 67(2): 730-737
URI: https://doi.org/10.1109/TED.2019.2960269
http://repository.iitr.ac.in/handle/123456789/22351
Issue Date: 2020
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Bandgap
compact model
density of states (DOS)
dimension
effective mass
gate-all-around
nanosheet
nanowire
quantum capacitance
SPICE
subband energy
ISSN: 189383
Author Scopus IDs: 56389226300
57014898700
56149406100
53866052200
57201524601
8544299000
14029622100
35594318600
Author Affiliations: Dasgupta, A., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-2284, United States
Parihar, S.S., Department of Electrical Engineering, IIT Kanpur, Kanpur, 208016, India
Kushwaha, P., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-2284, United States
Agarwal, H., Department of Electrical Engineering, IIT Jodhpur, Jodhpur, 342037, India
Kao, M.-Y., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-2284, United States
Salahuddin, S., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-2284, United States
Chauhan, Y.S., Department of Electrical Engineering, IIT Kanpur, Kanpur, 208016, India
Hu, C., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-2284, United States
Funding Details: Manuscript received September 27, 2019; revised November 25, 2019; accepted December 13, 2019. Date of publication January 10, 2020; date of current version January 27, 2020. This work was supported by the Berkeley Device Modeling Center and the Department of Science and Technology, India. The review of this article was arranged by Editor B. Iñiguez. (Corresponding author: Avirup Dasgupta.) A. Dasgupta, P. Kushwaha, M.-Y. Kao, S. Salahuddin, and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-2284 USA (e-mail: avirup@berkeley.edu). Department of Science and Technology, Ministry of Science and Technology, India, डीएसटी
Corresponding Author: Dasgupta, A.; Department of Electrical Engineering and Computer Sciences, United States; email: avirup@berkeley.edu
Appears in Collections:Journal Publications [ECE]

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