http://repository.iitr.ac.in/handle/123456789/22349| Title: | Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations |
| Authors: | Dabhi C.K. Parihar S.S. Dasgupta, Avirup Chauhan Y.S. |
| Published in: | IEEE Transactions on Electron Devices |
| Abstract: | The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal-ferroelectric-insulator-semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NC-FDSOI model is computationally efficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators. © 1963-2012 IEEE. |
| Citation: | IEEE Transactions on Electron Devices, 67(7): 2710-2716 |
| URI: | https://doi.org/10.1109/TED.2020.2994018 http://repository.iitr.ac.in/handle/123456789/22349 |
| Issue Date: | 2020 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Keywords: | BSIM-IMG compact model FDSOI MOSFETs ferroelectric (FE) metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance (NC) FET ultrathin-body silicon-on-insulator (UTBSOI) |
| ISSN: | 189383 |
| Author Scopus IDs: | 57200141180 57014898700 56389226300 14029622100 |
| Author Affiliations: | Dabhi, C.K., Department of Electrical Engineering, IIT Kanpur, Kanpur, 208016, India Parihar, S.S., Department of Electrical Engineering, IIT Kanpur, Kanpur, 208016, India Dasgupta, A., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, United States Chauhan, Y.S., Department of Electrical Engineering, IIT Kanpur, Kanpur, 208016, India |
| Funding Details: | Manuscript received January 14, 2020; revised April 8, 2020 and May 3, 2020; accepted May 6, 2020. Date of publication May 29, 2020; date of current version June 19, 2020. This work was supported in part by the Swarnajayanti Fellowship and FIST Scheme of the Department of Science and Technology and in part by the Berkeley Device Modeling Center (BDMC). The review of this article was arranged by Editor A. J. Scholten. (Corresponding author: Chetan Kumar Dabhi.) Chetan Kumar Dabhi, Shivendra Singh Parihar, and Yogesh Singh Chauhan are with the Department of Electrical Engineering, IIT Kanpur, Kanpur 208016, India (e-mail: chetant@iitk.ac.in; chauhan@iitk.ac.in). Department of Science and Technology, Government of Kerala |
| Corresponding Author: | Dabhi, C.K.; Department of Electrical Engineering, India; email: chetant@iitk.ac.in |
| Appears in Collections: | Journal Publications [ECE] |
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