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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/17851
Title: Design of low power two bit magnitude comparator using adiabatic logic
Authors: Kumar D.
Kumar M.
Published in: Proceedings of 2016 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2016
Abstract: This paper reports a new design of low power two bit magnitude comparator with adiabatic logic in 0.18μm CMOS technology. The proposed design shows the improvement in power delay product (PDP) of 66.76% to 82.97% with varying power supply for 1.1V to 2.0V as compared to conventional design. PDP of proposed design shows an improvement of 73.98% to 81.15 % with temperature varying from 50°C to 10°C as compared to conventional design. Results show a significant improvement in terms of PDP for proposed design as compared to existing conventional designs. © 2016 IEEE.
Citation: Proceedings of 2016 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2016, (2017)
URI: https://doi.org/10.1109/ISPACS.2016.7824703
http://repository.iitr.ac.in/handle/123456789/17851
Issue Date: 2017
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Adiabatic logic
domino logic
gate diffusion input
magnitude comparator
ISBN: 9.78E+12
Author Scopus IDs: 57202478211
55598963800
Author Affiliations: Kumar, D., USICT, Guru Gobind Singh Indraprastha University, Sector 16 C, Dwarka, New Delhi, 110078, India
Kumar, M., USICT, Guru Gobind Singh Indraprastha University, Sector 16 C, Dwarka, New Delhi, 110078, India
Appears in Collections:Conference Publications [ME]

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