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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/16254
Title: Investigation of intermediate dielectric for dual floating gate MOSFET
Authors: Sarkar, Biplab
Jayanti S.
Di Spigna N.
Lee B.
Misra V.
Franzon P.
Published in: Proceedings of 13th Non-Volatile Memory Technology Symposium, NVMTS 2013
Abstract: A dual floating gate transistor offers potential as a unified memory, with simultaneous volatile and non-volatile storage. The quality of the dielectric between the two floating gates is critical to achieving the required dynamic cycle endurance. This paper reports on the results of early experiments into the material choice and process for this dielectric. © 2013 IEEE.
Citation: Proceedings of 13th Non-Volatile Memory Technology Symposium, NVMTS 2013, (2013). Minneapolis, MN
URI: https://doi.org/10.1109/NVMTS.2013.6851052
http://repository.iitr.ac.in/handle/123456789/16254
Issue Date: 2013
Publisher: IEEE Computer Society
Keywords: DRAM
endurance
EOT
flash memory
floating gate
MIM
retention
ISBN: 9.78E+12
Author Scopus IDs: 57205868869
35770692200
6507948458
12802750500
7201897090
7006752280
Author Affiliations: Sarkar, B., Department of Electrical Engineering, North Carolina State University, Raleigh, NC 27606, United States
Jayanti, S., Department of Electrical Engineering, North Carolina State University, Raleigh, NC 27606, United States
Di Spigna, N., Department of Electrical Engineering, North Carolina State University, Raleigh, NC 27606, United States
Lee, B., Department of Electrical Engineering, North Carolina State University, Raleigh, NC 27606, United States
Misra, V., Department of Electrical Engineering, North Carolina State University, Raleigh, NC 27606, United States
Franzon, P., Department of Electrical Engineering, North Carolina State University, Raleigh, NC 27606, United States
Appears in Collections:Conference Publications [ECE]

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