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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/16246
Title: Warning prediction sequential for transient error prevention
Authors: Das B.P.
Onodera H.
Published in: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Abstract: Error Detection Sequential (EDS) is gaining enormous importance in timing error detection. In this work, we propose a warning detection scheme for sequential circuits which is very useful for dynamic, transient error prevention. The circuit consists of data edge detector, warning window generator and warning detector along with traditional Flip-flop. The delayed data is monitored during the warning window to flag a warning signal before the data enters the erroneous zone. We also propose an area-efficient edge detector which reduces the area of the proposed FF substantially. The proposed circuit can be used in Dynamic Voltage Scaling (DVS) for low power application and helps in determining when to stop further reduction in supply voltage. It is also useful in avoiding delay degradation due to aging. The feasibility of the circuit is simulated in industrial 65nm technology node. © 2010 IEEE.
Citation: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, (2010), 382- 390. Kyoto
URI: https://doi.org/10.1109/DFT.2010.52
http://repository.iitr.ac.in/handle/123456789/16246
Issue Date: 2010
Keywords: Aging circuit
Dynamic Voltage Scaling(DVS)
Error Detection Sequential(EDS)
Warning prediction sequential
ISBN: 9.78E+12
ISSN: 15505774
Author Scopus IDs: 24472836100
7202438710
Author Affiliations: Das, B.P., Graduate School of Informatics, Kyoto University, Japan
Onodera, H., Graduate School of Informatics, Kyoto University, Japan, JST, CREST, Japan
Corresponding Author: Das, B. P.; Graduate School of Informatics, Kyoto UniversityJapan; email: bishnu.iisc@gmail.com
Appears in Collections:Conference Publications [ECE]

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