Skip navigation
Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/16238
Title: Terminating load dependent width optimization of global inductive VLSI interconnects
Authors: Kumar Kaushik, Brajesh
Sarkar S.
Agarwal R.P.
Published in: Proceedings of IEEE 2005 International Conference on Emerging Technologies, ICET 2005
Abstract: In this paper interconnect width is optimized for a matched condition to reduce Power and Delay parameters. Width optimization is done for two sets of interconnect terminating conditions viz, 1) by active gate, and 2) by passive capacitance. For a driver interconnect load model terminated by an active gate, a tradeoff exists between short circuit and dynamic power in inductive interconnects, since with wider lines dynamic power increases, but short circuit power of the load gate decreases due to reduced transient delay. Whereas, for a line terminated by a capacitor, such tradeoff does not exist. The power consumption continues to increase even with reduced transient delay for wider lines. Many of the previous researches have modeled the active gate load at terminating end by its input parasitic gate capacitance. This paper shows that such modeling leads to inaccuracy in estimation of power, and therefore non-optimal width selection, especially for large fan-out conditions. © 2005 IEEE.
Citation: Proceedings of IEEE 2005 International Conference on Emerging Technologies, ICET 2005, (2005), 301- 305. Islamabad
URI: https://doi.org/10.1109/ICET.2005.1558898
http://repository.iitr.ac.in/handle/123456789/16238
Issue Date: 2005
Keywords: Inductive interconnects
Transient delay
VLSI interconnects
Capacitance
Capacitors
Optimization
Short circuit currents
Transients
VLSI circuits
ISBN: 0780392477; 9780780392472
Author Scopus IDs: 57021830600
7403239706
7402481365
Author Affiliations: Kaushik, B.K., Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee-247667, India
Sarkar, S., Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee-247667, India
Agarwal, R.P., IEEE, India, Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee-247667, India
Corresponding Author: Kaushik, B.K.; Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee-247667, India; email: bkk10dec@iitr.ernet.in
Appears in Collections:Conference Publications [ECE]

Files in This Item:
There are no files associated with this item.
Show full item record


Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.