Waveform analysis and delay prediction in simultaneously switching CMOS gate driven inductively and capacitively coupled on-chip interconnects

Abstract

This paper focuses on waveform analysis and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Delays at far-end of victim are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase and out-of-phase. Alpha Power Law model of MOS-transistor is used to represent the transistors in CMOS-driver. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures 90% propagation delay; transition time delay and waveform shape with good accuracy. © 2007 IEEE.