http://repository.iitr.ac.in/handle/123456789/16141
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kumar R. | - |
dc.contributor.author | Kumar Kaushik, Brajesh | - |
dc.contributor.author | Balasubramanian R. | - |
dc.contributor.editor | Tescher A.G. | - |
dc.date.accessioned | 2020-12-02T14:15:42Z | - |
dc.date.available | 2020-12-02T14:15:42Z | - |
dc.date.issued | 2017 | - |
dc.identifier.citation | Proceedings of SPIE - The International Society for Optical Engineering, (2017) | - |
dc.identifier.isbn | 9.78E+12 | - |
dc.identifier.issn | 0277786X | - |
dc.identifier.uri | https://doi.org/10.1117/12.2274682 | - |
dc.identifier.uri | http://repository.iitr.ac.in/handle/123456789/16141 | - |
dc.description.abstract | Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K-BRAM, 97 DSP-48, 6508 FFs and 8159 LUTs. © 2017 SPIE. | - |
dc.description.sponsorship | The Society of Photo-Optical Instrumentation Engineers (SPIE) | - |
dc.language.iso | en_US | - |
dc.publisher | SPIE | - |
dc.relation.ispartof | Proceedings of SPIE - The International Society for Optical Engineering | - |
dc.subject | FPGA | - |
dc.subject | HDMI input/output | - |
dc.subject | image dehazing | - |
dc.subject | video processing | - |
dc.subject | Xilinx high level synthesis (HLS) library | - |
dc.title | FPGA implementation of image dehazing algorithm for real time applications | - |
dc.type | Conference Paper | - |
dc.scopusid | 57211197963 | - |
dc.scopusid | 57021830600 | - |
dc.scopusid | 7103127999 | - |
dc.affiliation | Kumar, R., Department of Electronics and Communication Engineering, India | - |
dc.affiliation | Kaushik, B.K., Department of Electronics and Communication Engineering, India | - |
dc.affiliation | Balasubramanian, R., Department of Computer Science and Engineering, Indian Institute of Technology, Roorkee, 247667, India | - |
dc.identifier.conferencedetails | Applications of Digital Image Processing XL 2017, 7-10 August 2017 | - |
Appears in Collections: | Conference Publications [ECE] |
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