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Please use this identifier to cite or link to this item: http://repository.iitr.ac.in/handle/123456789/11113
Title: Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs
Authors: Kumar D.
Kumar M.
Published in: Microprocessors and Microsystems
Abstract: In a deep sub-micrometer regime as the scaling improves (reduction in feature size), gate oxide becomes thin and threshold voltage gets reduced, and thus the contribution in power dissipation due to leakage currents increases. Consequently, leakage currents in small feature size devices become a critical factor for low power applications. As the feature size has been reduced very much already, therefore it becomes very important to identify new techniques for power reduction instead of decreasing the feature size. Energy recovery technique is such a prominent technique which recycles the stored charge at different nodes and reduces power dissipation significantly. This paper reviews various energy recovery techniques based on different adiabatic logics. Analysis and comparison of different adiabatic logic techniques based on various parameters such as, the frequency of operation, µm technology used, supply voltage, the number of devices used has been done successfully in this paper. This paper explores various aspects of energy recovery logics. © 2018 Elsevier B.V.
Citation: Microprocessors and Microsystems (2018), 60(): 107-121
URI: https://doi.org/10.1016/j.micpro.2018.04.008
http://repository.iitr.ac.in/handle/123456789/11113
Issue Date: 2018
Publisher: Elsevier B.V.
ISSN: 1419331
Author Scopus IDs: 57202478211
55598963800
Author Affiliations: Kumar, D., USICT, Guru Gobind Singh Indraprastha University, Sector 16 C, Dwarka, New Delhi, 110078, India
Kumar, M., USICT, Guru Gobind Singh Indraprastha University, Sector 16 C, Dwarka, New Delhi, 110078, India
Funding Details: This research work has been supported by Ministry of Electronics & Information Technology (MeitY) Government of India (Visvesvaraya PhD Scheme), and Guru Gobind Singh Indraprastha University Delhi , India, with award letter number IPU/USICT/2015/3209 . We thank our colleagues from USICT, GGSIPU who provided insight and expertise that greatly assisted the research, although they may not agree with all of the interpretations/conclusions of this paper. Dinesh Kumar is working as a Research scholar in USICT (ECE), GGSIPU, Dwarka, New Delhi. He has experience of 3+ years in teaching and research. He has served Vivekananda college of Technology and Management Aligarh, UP, India for 2 years. He has completed M.Tech from Department of Electronics & Communication Engineering, National Institute of Technology, Kurukshetra, Haryana, India. He has published research papers in reputed International journals/conferences/symposiums. His research interests include digital logic design, low power CMOS circuits. Currently he is working actively on adiabatic logic circuits for low power CMOS based applications. Manoj Kumar is working as an Associate Professor in USICT (ECE), GGSIPU, Dwarka, New Delhi. He has experience of 11 years in teaching and research. He has served GJUST, Hisar, India for 07 years. He has completed Ph.D from Department of ECE, GJUST, Hisar, India. He has published more than 55 research papers in International/National journals and in reputed conferences/symposiums. He has guided 25 M. Tech students and presently four Ph.D students are working under his guidance. His research interests include integrated circuit design, low power CMOS system and microelectronics for communication systems. He is a Life Member of IETE (India), ISTE (India) and Semiconductor Society of India.
Corresponding Author: Kumar, D.; USICT, Guru Gobind Singh Indraprastha University, Sector 16 C, Dwarka, India; email: dinesh4saini@gmail.com
Appears in Collections:Journal Publications [ME]

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