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Showing results 1 to 16 of 16
Issue DateTitleAuthor(s)
2010An analytical approach to dynamic crosstalk in coupled interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2006Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2008Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnectsKumar Kaushik, Brajesh; Sarkar S.
2008Crosstalk analysis for a CMOS-gate-driven coupled interconnectsKumar Kaushik, Brajesh; Sarkar S.
2007Crosstalk analysis of an inductively and capacitively coupled interconnect driven by a CMOS gateKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2007Crosstalk analysis of simultaneously switching coupled interconnects driven by unipolar inputs through heterogeneous resistive driversKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2009Crosstalk analysis of simultaneously switching interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2011Effect of driver size and number of shells on propagation delay in MWCNT interconnectsDuksh Y.S.; Kumar Kaushik, Brajesh; Sarkar S.; Singh R.
2007Effect of line resistance and driver width on crosstalk in coupled VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2010Performance comparison of carbon nanotube, nickel silicide nanowire and copper VLSI interconnects: Perspectives and challenges aheadDuksh Y.S.; Kumar Kaushik, Brajesh; Sarkar S.; Singh R.
2011Repeater insertion in crosstalk-aware inductively and capacitively coupled interconnectsKumar Kaushik, Brajesh; Agarwal R.P.; Sarkar S.; Joshi R.C.; Chauhan D.S.
2005Terminating load dependent width optimization of global inductive VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.
2007Voltage scaling - A novel approach for crosstalk reduction in global VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2007Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect loadKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.
2007Waveform analysis and delay prediction in simultaneously switching CMOS gate driven inductively and capacitively coupled on-chip interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2006Width optimization of global inductive VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.