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Browsing by Author Scopus IDs 7402481365

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Issue DateTitleAuthor(s)
2010A new approach for testing CMOS circuits for glitchesSaxena A.; Kumar Kaushik, Brajesh; Agarwal R.P.; Kumar P.; Sharma K.
2010An analytical approach to dynamic crosstalk in coupled interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2011Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tiedindependent gate and symmetricasymmetric optionsVaddi R.; Agarwal R.P.; Dasgupta, Sudeb
2010Analytical potential distribution model for underlap double gate MOSFETs with 3T-4T and symmetric-asymmetric options for subthreshold operation: A conformal mapping approachVaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2012Compact modeling of a generic double-gate MOSFET with gate-S/D underlap for subthreshold operationVaddi R.; Agarwal R.P.; Dasgupta, Sudeb
2006Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2007Crosstalk analysis of an inductively and capacitively coupled interconnect driven by a CMOS gateKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2007Crosstalk analysis of simultaneously switching coupled interconnects driven by unipolar inputs through heterogeneous resistive driversKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2009Crosstalk analysis of simultaneously switching interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2011Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID): Device and circuit co-designVaddi R.; Agarwal R.P.; Dasgupta, Sudeb; Kim T.T.
2011Design and implementation of CORDIC processor for complex DPLLMandal A.; Kumar Kaushik, Brajesh; Kumar B.; Agarwal R.P.
2010Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOSVaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2009Device and circuit design challenges in the digital subthreshold region for ultralow-power applicationsVaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2011Effect of gate - S/D underlap, asymmetric and independent gate features in the minimization of short channel effects in nanoscale DGMOSFETVaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2007Effect of line resistance and driver width on crosstalk in coupled VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2015FDTD technique based crosstalk analysis of bundled SWCNT interconnectsDuksh Y.S.; Kumar Kaushik, Brajesh; Agarwal R.P.
2011Implementation of adaptive FIR filter for pulse doppler radarMandal A.; Kumar Kaushik, Brajesh; Kumar B.; Agarwal R.P.
2010Implementation of coordinate rotation algorithm for Digital Phase Locked Loop system in in-phase and quadrature channel signal processingMandal A.; Kumar Kaushik, Brajesh; Tyagi K.C.; Agarwal R.P.; Kumar A.
2009Investigation of robustness and performance comparisons of 3T - 4T DG-FinFETs for ultra low power subthreshold logicVaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2011Repeater insertion in crosstalk-aware inductively and capacitively coupled interconnectsKumar Kaushik, Brajesh; Agarwal R.P.; Sarkar S.; Joshi R.C.; Chauhan D.S.
Showing results 1 to 20 of 30  next >