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Showing results 1 to 20 of 118
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Issue Date
Title
Author(s)
2016
A compact half-wave folded waveguide resonator for dual-band applications
Snehalatha L.
;
Pathak, Nagendra Prasad
;
Manhas, Sanjeev Kumar
2016
A compact ridge cavity resonator for concurrent dual-band applications
Snehalatha L.
;
Pathak, Nagendra Prasad
;
Manhas, Sanjeev Kumar
2014
A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers
Shankar R.
;
Kaushal G.
;
Maheshwaram S.
;
Dasgupta, Sudeb
;
Manhas, Sanjeev Kumar
2010
A high performance vertical Si nanowire CMOS for ultra high density circuits
Maheshwaram S.
;
Kaushal G.
;
Manhas, Sanjeev Kumar
2014
A novel single cavity non-degenerate dual-mode dual-band resonator
Snehalatha L.
;
Pathak, Nagendra Prasad
;
Manhas, Sanjeev Kumar
;
Mukherjea S.
;
Krishnaswamy D.
;
Mueller P.
;
Comer D.E.
;
Mallick B.
;
Sikora A.
;
Thampi S.M.
2017
A reconfigurable dual-beam planar antenna with beam switching capability
Lalithamma S.
;
Pathak, Nagendra Prasad
;
Manhas, Sanjeev Kumar
2016
A simple method for detection of anionic detergents in milk using unmodified gold nanoparticles
Kumar P.
;
Kumar P.
;
Manhas, Sanjeev Kumar
;
Navani, Naveen Kumar
2012
A simulation study of the effect of platinum contact on CNT based gas sensors using self-consistent field with NEGF method
Basak A.
;
Manhas S.K.
;
Kapil G.
;
Dasgupta, Sudeb
;
Jain N.
2017
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation
Prakash O.
;
Maheshwaram S.
;
Sharma M.
;
Anand, Bulusu
;
Saxena A.K.
;
Manhas, Sanjeev Kumar
2017
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation
Prakash O.
;
Maheshwaram S.
;
Sharma M.
;
Anand, Bulusu
;
Saxena A.K.
;
Manhas S.K.
2016
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization
Kaur B.
;
Sharma A.
;
Alam N.
;
Manhas, Sanjeev Kumar
;
Anand, Bulusu
2016
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization
Kaur B.
;
Sharma A.
;
Alam N.
;
Manhas S.K.
;
Anand, Bulusu
2019
Altering the Schottky Barrier Height and Conductance by Using Metal Nanoparticles in Carbon Nanotubes-Based Devices
Kumar N.
;
Navani, Naveen Kumar
;
Manhas, Sanjeev Kumar
2015
An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications
Joshi A.
;
Manhas, Sanjeev Kumar
;
Sharma S.K.
;
Dasgupta S.
2015
An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications
Joshi A.
;
Manhas S.K.
;
Sharma S.K.
;
Dasgupta, Sudeb
2012
An accurate current source model for CMOS based combinational logic cell
Kaur B.
;
Vundavalli S.
;
Manhas, Sanjeev Kumar
;
Dasgupta, Sudeb
;
Anand, Bulusu
2012
An accurate current source model for CMOS based combinational logic cell
Kaur B.
;
Vundavalli S.
;
Manhas S.K.
;
Dasgupta S.
;
Anand, Bulusu
2013
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies
Kaur B.
;
Miryala S.
;
Manhas, Sanjeev Kumar
;
Anand, Bulusu
2013
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies
Kaur B.
;
Miryala S.
;
Manhas S.K.
;
Anand, Bulusu
2012
Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects
Majumder M.K.
;
Pandya N.D.
;
Kumar Kaushik, Brajesh
;
Manhas, Sanjeev Kumar
