Skip navigation
Home
Browse
Communities
& Collections
Browse Items by:
Issue Date
Author
Title
Subject
Author Scopus IDs
Published In
Help
Sign on to:
My Repository
Receive email
updates
Edit Profile
IITR's Institutional Repository
Browsing by Author Scopus IDs 57191737302
Jump to:
0-9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
or enter first few letters:
Sort by:
title
issue date
submit date
In order:
Ascending
Descending
Results/Page
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Authors/Record:
All
1
5
10
15
20
25
30
35
40
45
50
Showing results 1 to 20 of 223
next >
Issue Date
Title
Author(s)
2017
6T SRAM cell analysis for DRV and read stability
Ruchi
;
Dasgupta, Sudeb
2009
A 1.2 volt, 90nm, 16-Bit three way segmented digital to analog converter (DAC) for low power applications
Chandrasekhar M.
;
Dasgupta, Sudeb
2004
A compact analytical model for a gaussian doped nanoscale MOSFET and evidence for diminished Short Channel Effects
Datta D.
;
Dasgupta, Sudeb
2008
A compact drain current and threshold voltage quantum mechanical analytical modeling for FinFETs
Raj B.
;
Saxena A.K.
;
Dasgupta, Sudeb
2018
A compact physics-based surface potential and drain current model for an S/D Spacer-Based DG-RFET
Bhattacharjee A.
;
Dasgupta, Sudeb
2015
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives
Pal P.K.
;
Kaushik B.K.
;
Anand, Bulusu
;
Dasgupta S.
2015
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives
Pal P.K.
;
Kaushik B.K.
;
Anand B.
;
Dasgupta, Sudeb
2009
A comparative study of 6T, 8T and 9T decanano SRAM cell
Athe P.
;
Dasgupta, Sudeb
2014
A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers
Shankar R.
;
Kaushal G.
;
Maheshwaram S.
;
Dasgupta, Sudeb
;
Manhas, Sanjeev Kumar
2016
A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metrics
Pal P.K.
;
Kumar Kaushik, Brajesh
;
Dasgupta, Sudeb
2017
A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET
Bhattacharjee A.
;
Saikiran M.
;
Dasgupta, Sudeb
2019
A Hybridized Fuzzy-Neural Predictive Intelligent (HFNPI) Modelling Approach-based Underlap FinFET Model
Sharma S.M.
;
Dasgupta, Sudeb
;
Kartikeyan, Machavaram Venkata
2011
A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier
Rathod S.S.
;
Saxena A.K.
;
Dasgupta, Sudeb
2013
A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits
Singh S.
;
Kumar Kaushik, Brajesh
;
Dasgupta, Sudeb
2021
A Novel High RSNM RHBD 16T SRAM Cell at 180nm
Prakash B.S.
;
Yadav A.
;
Anand, Bulusu
;
Dasgupta S.
2021
A Novel High RSNM RHBD 16T SRAM Cell at 180nm
Prakash B.S.
;
Yadav A.
;
Bulusu A.
;
Dasgupta, Sudeb
2019
A Novel Twofold Tunnel FET with Reduced Miller Capacitance: Proposal and Investigation
Bagga N.
;
Chauhan N.
;
Gupta D.
;
Dasgupta, Sudeb
2017
A novel VDSAT extraction method for tunnel FETs and its implication on analog design
Acharya A.
;
Dasgupta, Sudeb
;
Anand, Bulusu
2017
A novel VDSAT extraction method for tunnel FETs and its implication on analog design
Acharya A.
;
Dasgupta S.
;
Anand, Bulusu
2010
A proposed DG-FinFET based SRAM cell design with RadHard capabilities
Rathod S.S.
;
Saxena A.K.
;
Dasgupta, Sudeb
