| Issue Date | Title | Author(s) |
| 2015 | A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives | Pal P.K.; Kumar Kaushik, Brajesh; Anand, Bulusu; Dasgupta S. |
| 2015 | A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives | Pal P.K.; Kaushik B.K.; Anand, Bulusu; Dasgupta S. |
| 2015 | A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives | Pal P.K.; Kaushik B.K.; Anand B.; Dasgupta, Sudeb |
| 2016 | A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metrics | Pal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2015 | Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis | Pal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2014 | Design metrics improvement for SRAMs using symmetric dual-k spacer (SymD-k) FinFETs | Pal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2015 | Enhanced device performance using lightly doped channel junctionless accumulation-mode FinFET | Pal P.K.; Nehra D.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2014 | High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications | Nehra D.; Pal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2013 | High-performance and robust SRAM cell based on asymmetric dual-k spacer Finfets | Pal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2015 | Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOS | Mahawar S.; Verma S.; Pal P.K.; Kumar Kaushik, Brajesh |
| 2014 | Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective | Pal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2014 | Low-power and robust 6T SRAM cell using symmetric dual-k spacer FinFETs | Pal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2013 | Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers | Pal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
| 2012 | Performance analysis of dual-k spacer at source side for underlap FinFETs | Pal P.K.; Singh P.; Kumar Kaushik, Brajesh; Anand, Bulusu; Dasgupta S. |
| 2012 | Performance analysis of dual-k spacer at source side for underlap FinFETs | Pal P.K.; Singh P.; Kaushik B.K.; Anand B.; Dasgupta, Sudeb |
| 2012 | Performance analysis of dual-k spacer at source side for underlap FinFETs | Pal P.K.; Singh P.; Kaushik B.K.; Anand, Bulusu; Dasgupta S. |
| 2016 | Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-Spacer NMOS | Verma S.; Pal P.K.; Mahawar S.; Kumar Kaushik, Brajesh |
| 2015 | Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design | Pal P.K.; Verma S.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb |
