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Showing results 1 to 20 of 35  next >
Issue DateTitleAuthor(s)
2016A novel energy-efficient self-correcting methodology employing INWEKumar C.I.; Sharma A.; Miryala S.; Anand, Bulusu
2021A physical insight into variation aware minimum v DDfor deep subthreshold operation of FinFETYadav S.; Chauhan N.; Tyagi S.; Sharma A.; Banchhor S.; Joshi R.; Pratap R.; Anand, Bulusu
2021A physical insight into variation aware minimum v DDfor deep subthreshold operation of FinFETYadav S.; Chauhan N.; Tyagi S.; Sharma A.; Banchhor S.; Joshi R.; Pratap R.; Anand, Bulusu
2019A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage LatchesKumar C.I.; Bhatia I.; Sharma A.K.; Sehgal D.; Jatana H.S.; Anand, Bulusu
2019A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage LatchesKumar C.I.; Bhatia I.; Sharma A.K.; Sehgal D.; Jatana H.S.; Anand, Bulusu
2016A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterizationKaur B.; Sharma A.; Alam N.; Manhas, Sanjeev Kumar; Anand, Bulusu
2016A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterizationKaur B.; Sharma A.; Alam N.; Manhas S.K.; Anand, Bulusu
2016An efficient methodology to characterize the TSPC flip flop setup time for static timing analysisVarma S.S.; Sharma A.; Anand, Bulusu
2014An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity EffectDalai B.K.; Karnnan N.; Sharma A.; Anand, Bulusu
2019An energy-efficient variation aware self-correcting latchKumar C.I.; Sharma A.K.; Partap R.; Anand, Bulusu
2019An energy-efficient variation aware self-correcting latchKumar C.I.; Sharma A.K.; Partap R.; Anand, Bulusu
2017Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit DesignSharma A.; Alam N.; Anand, Bulusu
2017Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit DesignSharma A.; Alam N.; Anand, Bulusu
2018Effective Drive Current for Near-Threshold CMOS Circuits' Performance Evaluation: Modeling to Circuit Design TechniquesSharma A.; Alam N.; Anand, Bulusu
2018Effective Drive Current for Near-Threshold CMOS Circuits' Performance Evaluation: Modeling to Circuit Design TechniquesSharma A.; Alam N.; Anand, Bulusu
2015Efficient static D-latch standard cell characterization using a novel setup time modelSharma A.; Sharma Y.; Dasgupta S.; Anand, Bulusu
2015Efficient static D-latch standard cell characterization using a novel setup time modelSharma A.; Sharma Y.; Dasgupta, Sudeb; Anand B.
2021Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FETGarg C.; Chauhan N.; Sharma A.; Banchhor S.; Doneria A.; Dasgupta, Sudeb; Anand, Bulusu
2021Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FETGarg C.; Chauhan N.; Sharma A.; Banchhor S.; Doneria A.; Dasgupta S.; Anand, Bulusu
2018Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structureSharma A.; Alam N.; Chawla R.; Anand, Bulusu