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Browsing by Author Scopus IDs 42161683700

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Showing results 1 to 20 of 36  next >
Issue DateTitleAuthor(s)
2014A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriersShankar R.; Kaushal G.; Maheshwaram S.; Dasgupta, Sudeb; Manhas, Sanjeev Kumar
2010A high performance vertical Si nanowire CMOS for ultra high density circuitsMaheshwaram S.; Kaushal G.; Manhas, Sanjeev Kumar
2017A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulationPrakash O.; Maheshwaram S.; Sharma M.; Anand, Bulusu; Saxena A.K.; Manhas, Sanjeev Kumar
2017A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulationPrakash O.; Maheshwaram S.; Sharma M.; Anand, Bulusu; Saxena A.K.; Manhas S.K.
2016Compact model for vertical silicon nanowire based device simulation and circuit designSharma M.; Maheshwaram S.; Prakash O.; Anand, Bulusu; Saxena A.K.; Manhas, Sanjeev Kumar
2017Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuitsPrakash O.; Beniwal S.; Maheshwaram S.; Anand, Bulusu; Singh N.; Manhas, Sanjeev Kumar
2017Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuitsPrakash O.; Beniwal S.; Maheshwaram S.; Anand, Bulusu; Singh N.; Manhas S.K.
2012Device circuit co-design issues in vertical nanowire CMOS platformMaheshwaram S.; Manhas, Sanjeev Kumar; Kaushal G.; Anand, Bulusu; Singh N.
2012Device circuit co-design issues in vertical nanowire CMOS platformMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand, Bulusu; Singh N.
2013Drive matching issues in multi gate CMOS inverterKaushal G.; Maheshwaram S.; Dasgupta, Sudeb; Manhas, Sanjeev Kumar
2014Effect of load capacitance and input transition time on FinFET inverter capacitancesPandey A.; Raycha S.; Maheshwaram S.; Manhas, Sanjeev Kumar; Dasgupta, Sudeb; Saxena A.K.; Anand, Bulusu
2014Effect of load capacitance and input transition time on FinFET inverter capacitancesPandey A.; Raycha S.; Maheshwaram S.; Manhas S.K.; Dasgupta S.; Saxena A.K.; Anand, Bulusu
2013FinFET device capacitances: Impact of input transition time and output loadPandey A.; Raycha S.; Maheshwaram S.; Manhas, Sanjeev Kumar; Dasgupta, Sudeb; Saxena A.K.; Anand, Bulusu
2013FinFET device capacitances: Impact of input transition time and output loadPandey A.; Raycha S.; Maheshwaram S.; Manhas S.K.; Dasgupta S.; Saxena A.K.; Anand, Bulusu
2013Impact of series resistance on Si nanowire MOSFET performanceKaushal G.; Manhas, Sanjeev Kumar; Maheshwaram S.; Dasgupta S.
2013Impact of series resistance on Si nanowire MOSFET performanceKaushal G.; Manhas S.K.; Maheshwaram S.; Dasgupta, Sudeb
2017Lateral silicon nanowire based standard cell design for higher performancePrakash O.; Sharma M.; Anand, Bulusu; Saxena A.K.; Manhas, Sanjeev Kumar; Maheshwaram S.
2017Lateral silicon nanowire based standard cell design for higher performancePrakash O.; Sharma M.; Anand, Bulusu; Saxena A.K.; Manhas S.K.; Maheshwaram S.
2015Low power SRAM design for 14 nm GAA Si-nanowire technologyKaushal G.; Jeong H.; Maheshwaram S.; Manhas, Sanjeev Kumar; Dasgupta, Sudeb; Jung S.O.
2014Novel design methodology using LEXT sizing in nanowire CMOS logicKaushal G.; Manhas, Sanjeev Kumar; Maheshwaram S.; Anand, Bulusu; Dasgupta, Sudeb; Singh N.
Showing results 1 to 20 of 36  next >