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Showing results 1 to 19 of 19
Issue DateTitleAuthor(s)
2020Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FETKao M.-Y.; Pahwa G.; Dasgupta, Avirup; Salahuddin S.; Hu C.
2020BSIM compact model of quantum confinement in advanced nanosheet FETsDasgupta, Avirup; Parihar S.S.; Kushwaha P.; Agarwal H.; Kao M.-Y.; Salahuddin S.; Chauhan Y.S.; Hu C.
2015BSIM-CMG: Standard FinFET compact model for advanced circuit designDuarte J.P.; Khandelwal S.; Medury A.; Hu C.; Kushwaha P.; Agarwal H.; Dasgupta, Avirup; Chauhan Y.S.; Dielacher F.; Pribyl W.; Hueber G.
2020BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel InversionAgarwal H.; Kushwaha P.; Dasgupta, Avirup; Y-Kao M.; Morshed T.; Workman G.; Shanbhag K.; Li X.; Vinothkumar V.; Chauhan Y.S.; Salahuddin S.; Hu C.
2019Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology NodeKushwaha P.; Agarwal H.; Lin Y.-K.; Dasgupta, Avirup; Kao M.-Y.; Lu Y.; Yue Y.; Chen X.; Wang J.; Sy W.; Yang F.; Chidambaram P.R.C.; Salahuddin S.; Hu C.
2016Characterization of RF Noise in UTBB FD-SOI MOSFETKushwaha P.; Dasgupta, Avirup; Sahu Y.; Khandelwal S.; Hu C.; Chauhan Y.S.
2020Compact Model for Geometry Dependent Mobility in Nanosheet FETsDasgupta, Avirup; Parihar S.S.; Agarwal H.; Kushwaha P.; Chauhan Y.S.; Hu C.
2018Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D TransitionDasgupta, Avirup; Rastogi P.; Agarwal A.; Hu C.; Chauhan Y.S.
2017Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias EffectSahu Y.; Kushwaha P.; Dasgupta, Avirup; Hu C.; Chauhan Y.S.
2021Compact Modeling of Temperature Effects in FDSOI and FinFET Devices down to Cryogenic TemperaturesPahwa G.; Kushwaha P.; Dasgupta, Avirup; Salahuddin S.; Hu C.
2020Design Optimization Techniques in Nanosheet Transistor for RF ApplicationsKushwaha P.; Dasgupta, Avirup; Kao M.-Y.; Agarwal H.; Salahuddin S.; Hu C.
2021Energy Storage and Reuse in Negative CapacitanceKao M.-Y.; Liao Y.-H.; Pahwa G.; Dasgupta, Avirup; Salahuddin S.; Hu C.
2020Gate-All-Around FET Design Rule for Suppression of Excess Non-LinearityDasgupta, Avirup; Hu C.
2017Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETsDasgupta, Avirup; Gupta C.; Dutta A.; Lin Y.-K.; Srihari S.; Ethirajan T.; Hu C.; Chauhan Y.S.
2018Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFETDabhi C.K.; Dasgupta, Avirup; Kushwaha P.; Agarwal H.; Hu C.; Chauhan Y.S.
2019Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFETKushwaha P.; Agarwal H.; Mishra V.; Dasgupta, Avirup; Lin Y.-K.; Kao M.-Y.; Chauhan Y.S.; Salahuddin S.; Hu C.
2019Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the ChannelKao M.-Y.; Lin Y.-K.; Agarwal H.; Liao Y.-H.; Kushwaha P.; Dasgupta, Avirup; Salahuddin S.; Hu C.
2019Proposal for capacitance matching in negative capacitance field-effect transistorsAgarwal H.; Kushwaha P.; Lin Y.-K.; Kao M.-Y.; Liao Y.-H.; Dasgupta, Avirup; Salahuddin S.; Hu C.
2019Spacer Engineering in Negative Capacitance FinFETsLin Y.-K.; Agarwal H.; Kao M.-Y.; Zhou J.; Liao Y.-H.; Dasgupta, Avirup; Kushwaha P.; Salahuddin S.; Hu C.