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Issue DateTitleAuthor(s)
2016A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterizationKaur B.; Sharma A.; Alam N.; Manhas, Sanjeev Kumar; Anand, Bulusu
2016A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterizationKaur B.; Sharma A.; Alam N.; Manhas S.K.; Anand, Bulusu
2014An analytical delay model for mechanical stress induced systematic variability analysis in nanoscale circuit designAlam N.; Anand B.; Dasgupta, Sudeb
2014An analytical delay model for mechanical stress induced systematic variability analysis in nanoscale circuit designAlam N.; Anand, Bulusu; Dasgupta S.
2017Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit DesignSharma A.; Alam N.; Anand, Bulusu
2017Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit DesignSharma A.; Alam N.; Anand, Bulusu
2018Effective Drive Current for Near-Threshold CMOS Circuits' Performance Evaluation: Modeling to Circuit Design TechniquesSharma A.; Alam N.; Anand, Bulusu
2018Effective Drive Current for Near-Threshold CMOS Circuits' Performance Evaluation: Modeling to Circuit Design TechniquesSharma A.; Alam N.; Anand, Bulusu
2014Efficient ECSM characterization considering voltage, temperature, and mechanical stress variabilityKaur B.; Alam N.; Manhas, Sanjeev Kumar; Anand, Bulusu
2014Efficient ECSM characterization considering voltage, temperature, and mechanical stress variabilityKaur B.; Alam N.; Manhas S.K.; Anand, Bulusu
2012Gate-pitch optimization for circuit design using strain-engineered multifinger gate structuresAlam N.; Anand B.; Dasgupta, Sudeb
2012Gate-pitch optimization for circuit design using strain-engineered multifinger gate structuresAlam N.; Anand, Bulusu; Dasgupta S.
2012Impact of dummy poly on the process-induced mechanical stress enhanced circuit performanceAlam N.; Anand, Bulusu; Dasgupta S.
2012Impact of dummy poly on the process-induced mechanical stress enhanced circuit performanceAlam N.; Anand B.; Dasgupta, Sudeb
2018Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structureSharma A.; Alam N.; Chawla R.; Anand, Bulusu
2018Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structureSharma A.; Alam N.; Chawla R.; Anand, Bulusu
2016Multifinger MOSFETs' Optimization Considering Stress and INWE in Static CMOS CircuitsSharma A.; Alam N.; Dasgupta, Sudeb; Bulusu A.
2016Multifinger MOSFETs' Optimization Considering Stress and INWE in Static CMOS CircuitsSharma A.; Alam N.; Dasgupta S.; Anand, Bulusu
2015Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologiesSharma A.K.; Mishra N.; Alam N.; Dasgupta S.; Anand, Bulusu
2015Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologiesSharma A.K.; Mishra N.; Alam N.; Dasgupta, Sudeb; Bulusu A.