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Issue Date	Title	Author(s)
2016	A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization	Kaur B.; Sharma A.; Alam N.; Manhas, Sanjeev Kumar; Anand, Bulusu
2016	A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization	Kaur B.; Sharma A.; Alam N.; Manhas S.K.; Anand, Bulusu
2014	An analytical delay model for mechanical stress induced systematic variability analysis in nanoscale circuit design	Alam N.; Anand B.; Dasgupta, Sudeb
2014	An analytical delay model for mechanical stress induced systematic variability analysis in nanoscale circuit design	Alam N.; Anand, Bulusu; Dasgupta S.
2017	Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design	Sharma A.; Alam N.; Anand, Bulusu
2017	Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design	Sharma A.; Alam N.; Anand, Bulusu
2018	Effective Drive Current for Near-Threshold CMOS Circuits' Performance Evaluation: Modeling to Circuit Design Techniques	Sharma A.; Alam N.; Anand, Bulusu
2018	Effective Drive Current for Near-Threshold CMOS Circuits' Performance Evaluation: Modeling to Circuit Design Techniques	Sharma A.; Alam N.; Anand, Bulusu
2014	Efficient ECSM characterization considering voltage, temperature, and mechanical stress variability	Kaur B.; Alam N.; Manhas, Sanjeev Kumar; Anand, Bulusu
2014	Efficient ECSM characterization considering voltage, temperature, and mechanical stress variability	Kaur B.; Alam N.; Manhas S.K.; Anand, Bulusu
2012	Gate-pitch optimization for circuit design using strain-engineered multifinger gate structures	Alam N.; Anand B.; Dasgupta, Sudeb
2012	Gate-pitch optimization for circuit design using strain-engineered multifinger gate structures	Alam N.; Anand, Bulusu; Dasgupta S.
2012	Impact of dummy poly on the process-induced mechanical stress enhanced circuit performance	Alam N.; Anand, Bulusu; Dasgupta S.
2012	Impact of dummy poly on the process-induced mechanical stress enhanced circuit performance	Alam N.; Anand B.; Dasgupta, Sudeb
2018	Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structure	Sharma A.; Alam N.; Chawla R.; Anand, Bulusu
2018	Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structure	Sharma A.; Alam N.; Chawla R.; Anand, Bulusu
2016	Multifinger MOSFETs' Optimization Considering Stress and INWE in Static CMOS Circuits	Sharma A.; Alam N.; Dasgupta, Sudeb; Bulusu A.
2016	Multifinger MOSFETs' Optimization Considering Stress and INWE in Static CMOS Circuits	Sharma A.; Alam N.; Dasgupta S.; Anand, Bulusu
2015	Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies	Sharma A.K.; Mishra N.; Alam N.; Dasgupta S.; Anand, Bulusu
2015	Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies	Sharma A.K.; Mishra N.; Alam N.; Dasgupta, Sudeb; Bulusu A.

Showing results 1 to 20 of 33 next >

Browsing by Author Scopus IDs 35114445600