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Showing results 1 to 20 of 28  next >
Issue DateTitleAuthor(s)
2016A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterizationKaur B.; Sharma A.; Alam N.; Manhas, Sanjeev Kumar; Anand, Bulusu
2016A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterizationKaur B.; Sharma A.; Alam N.; Manhas S.K.; Anand, Bulusu
2015An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applicationsJoshi A.; Manhas, Sanjeev Kumar; Sharma S.K.; Dasgupta S.
2015An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applicationsJoshi A.; Manhas S.K.; Sharma S.K.; Dasgupta, Sudeb
2014An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD methodKumar V.R.; Kumar Kaushik, Brajesh; Patnaik, Amalendu
2010An analytical approach to dynamic crosstalk in coupled interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2019An energy-efficient variation aware self-correcting latchKumar C.I.; Sharma A.K.; Partap R.; Anand, Bulusu
2019An energy-efficient variation aware self-correcting latchKumar C.I.; Sharma A.K.; Partap R.; Anand, Bulusu
2019An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applicationsSharma P.; Jain P.; Das, Bishnu Prasad
2013Analytical modeling and parameter extraction of top and bottom contact structures of organic thin film transistorsKumar B.; Kumar Kaushik, Brajesh; Negi, Yuvraj Singh; Saxena S.; Varma, Ghanshyam Das
2011Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tiedindependent gate and symmetricasymmetric optionsVaddi R.; Agarwal R.P.; Dasgupta, Sudeb
2013Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnectsKumar Kaushik, Brajesh; Agarwal D.; Babu N.G.
2012Channel length variation effect on performance parameters of organic field effect transistorsMittal P.; Kumar B.; Negi, Yuvraj Singh; Kumar Kaushik, Brajesh; Singh R.K.
2021Computing-in-memory using voltage-controlled spin-orbit torque based MRAM arrayShreya S.; Jain A.; Kumar Kaushik, Brajesh
2008Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnectsKumar Kaushik, Brajesh; Sarkar S.
2011Electrical performance study of 25 nm Ω-FinFET under the influence of gamma radiation: A 3D simulationRathod S.S.; Saxena A.K.; Dasgupta, Sudeb
2012Impact of dual-k spacer on analog performance of underlap FinFETNandi A.; Saxena A.K.; Dasgupta, Sudeb
2015Improved crosstalk noise modeling of MWCNT interconnects using FDTD techniqueKumar V.R.; Kumar Kumar Kaushik, Brajesh; Patnaik, Amalendu
2001Influence of ionising radiation on the performance of CMOS inverterChauhan R.K.; Dasgupta, Sudeb; Chakrabarti P.
2015Low power SRAM design for 14 nm GAA Si-nanowire technologyKaushal G.; Jeong H.; Maheshwaram S.; Manhas, Sanjeev Kumar; Dasgupta, Sudeb; Jung S.O.