| Issue Date | Title | Author(s) |
| 2014 | A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers | Shankar R.; Kaushal G.; Maheshwaram S.; Dasgupta, Sudeb; Manhas, Sanjeev Kumar |
| 2020 | A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design | Kumar C.I.; Anand, Bulusu |
| 2020 | A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design | Kumar C.I.; Anand, Bulusu |
| 2021 | A Thermal Circuit Representing Frequency Dependent Dynamic Heating between Electron and Lattice in SOI-FinFET | Kumar V.; Dasgupta, Sudeb; Datta, Arnab |
| 2017 | Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits | Prakash O.; Beniwal S.; Maheshwaram S.; Anand, Bulusu; Singh N.; Manhas, Sanjeev Kumar |
| 2017 | Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits | Prakash O.; Beniwal S.; Maheshwaram S.; Anand, Bulusu; Singh N.; Manhas S.K. |
| 2020 | Design and Analysis of Leakage-Induced False Error Tolerant Error Detecting Latch for Sub/Near-Threshold Applications | Sharma P.; Das, Bishnu Prasad |
| 2021 | Eight-Level/Cell Storage by Tuning the Spatial Distribution of Dielectrics in a Tri-Layer ReRAM Cell: Electrical Characteristics and Reliability | Vishwakarma K.; Kishore R.; Datta, Arnab |
| 2021 | Impact of Bias Temperature Stress on IGZO/Ni/IGZO Steep Subthreshold Vertical Current Driver Fabricated at Room Temperature | Kishore R.; Vishwakarma K.; Datta, Arnab |
| 2016 | Impact of Dielectric Resistive Heater, Bottom Contact and Reading Scheme on the Reliability of Nanoscale Low Power Phase Change Memory (PCM) Cell: 3-D-ADI Modeling | Jagtiani S.; Datta, Arnab |
| 2020 | Oxide edge trap density extraction in silicon nanowire MOSFET from tunnel current noise measurement in gated diode like arrangement | Kumar Sharma D.; Datta, Arnab |
