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Browsing by Author Verma K.G.

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Showing results 1 to 6 of 6

Issue Date	Title	Author(s)
2009	Effects of process variation in VLSI interconnects - A technical review	Verma K.G.; Kumar Kaushik, Brajesh; Singh R.
2011	Monte Carlo analysis of propagation delay due to process induced line parasitic variations in VLSI interconnects	Verma K.G.; Singh R.; Kumar Kaushik, Brajesh; Kumar B.
2011	Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects	Verma K.G.; Singh R.; Kumar Kaushik, Brajesh; Majumder M.K.
2011	Propagation delay deviations due to process tempted driver width variations	Verma K.G.; Kumar Kaushik, Brajesh; Singh R.; Kumar B.
2010	Propagation Delay Variation due to Process Induced Threshold Voltage Variation	Verma K.G.; Kumar Kaushik, Brajesh; Singh R.; Das V.; VVijaykumar R.; Srinivasa K.G.; Aboalsamh H.A.; Hammoudeh M.; Salmani V.; Tyagi D.K.; Mohapatra A.; Jaysimha B.; Ambikairajah E.; Blackledge J.
2010	Propagation delay variations under process deviation in driver interconnect load system	Verma K.G.; Kumar Kaushik, Brajesh; Singh R.

Showing results 1 to 6 of 6